參數(shù)資料
型號: PCA9698BS,118
廠商: NXP Semiconductors
文件頁數(shù): 15/48頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 40B 56HVQFN
產(chǎn)品培訓模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標準包裝: 1
接口: I²C
輸入/輸出數(shù): 40
中斷輸出:
頻率 - 時鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-HVQFN
包裝: 標準包裝
包括: POR
產(chǎn)品目錄頁面: 826 (CN2011-ZH PDF)
其它名稱: 568-3240-6
22
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
5.
Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6.
Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft-
ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set,
the CPU is halted for two cycles before the next instruction is executed.
Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 7-2 lists the typical pro-
gramming time for EEPROM access from the CPU.
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob-
ally) so that no interrupts will occur during execution of these functions. The examples also
assume that no Flash Boot Loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.
Table 7-2.
EEPROM Programming Time
Symbol
Number of Calibrated RC Oscillator Cycles
Typ Programming Time
EEPROM write
(from CPU)
26,368
3.3 ms
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