參數(shù)資料
型號(hào)： PCD6001H
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Digital telephone answering machine chip
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 71/96頁
文件大小： 385K
代理商： PCD6001H
2001 Apr 17
71
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6001
16 EXTERNAL I/O INTERFACES
16.1
External analog interfaces
16.1.1
G
ENERAL PURPOSE
ADC
AND
DAC
Forgeneraluse,forinstancebatterymanagement,parallel
set detection or speaker amplifier volume control, a 2-line
multiplexed 8-bit ADC and an 8-bit DAC are on-chip. The
ADC and the DAC consist of several analog sub-blocks
called AVS and AAD, which are controlled by the digital
block DCA (see Fig.33). Block AVS generates voltages in
a time multiplexed way, and acts as a DAC with the
bandgap voltage V
BGP
as input voltage. Block AAD
contains a comparator that is part of the successive
approximation ADC formed by a combination of AVS, AAD
and DCA. The analog-to-digital conversion can be
performed on two external input signals: AD0IN and
AD1IN.
The whole circuit is active as long as the chip is in
System-on mode. Both the ADC and the DAC can be
controlled by the microcontroller, the SFR mapped
DCA block allowing the user a flexible interface to analog
peripherals.
16.1.2
G
ENERAL PURPOSE
ADC
The on-chip ADC is a two channel multiplexed 8-bit
converter. The control of this converter is done via two bits
in the microcontroller GPADC SFR. One bit selects the
channel and the other bit is the converter request bit. The
request bit is reset by hardware when the converter has
finished its conversion cycle. The ADC (AAD in Fig.33), is
of the successive approximation type.
An internal register contains the value of the slider position
and is changed after each comparison of V
adc
with one of
the two possible analog-to-digital inputs (AD0IN and
AD1IN). After 8 comparisons the conversion is finished
and the contents of the internal register is copied into the
register GPADR. Total analog-to-digital conversion time
(from setting the Request bit until GPADR ready) is less
than50 ms.Thisregistercaninturnbereadbytheinternal
microcontroller.
16.1.2.1
General Purpose ADC Register (GPADC)
Table 64
General Purpose ADC Register (SFR address C3H); reset state 00H
Table 65
Description of GPADC bits
16.1.2.2
General Purpose ADC Result Register (GPADR)
This register holds the 8-bit result value from the conversion. The conversion range is 0 to 2000 mV (V
REF
) with 8 mV
resolution.
Table 66
General Purpose ADC Result Register (SFR address C2H); reset state 00H, read only
7
6
5
4
3
2
1
0
AADC
CS
REQCOM
BIT
SYMBOL
AADC
DESCRIPTION
7 to 3
2
These 5 bits are reserved.
Automatic Analog-to-Digital Conversion.
If AADC = 1, then a conversion is
performed every 30 ms, regardless of state of request confirm bit.
Channel Select.
If CS = 0, analog-to-digital conversion input is on pin AD0IN. If CS = 1,
analog-to-digital conversion input is on pin AD1IN. Switching of the analog-to-digital
channel is only allowed when no analog-to-digital conversion currently is in progress.
Otherwise the resulting value will be corrupt.
Request Confirm.
1
CS
0
REQCOM
7
6
5
4
3
2
1
0
A/D.7
A/D.6
A/D.5
A/D.4
A/D.3
A/D.2
A/D.1
A/D.0
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