參數(shù)資料
型號(hào)： PCF51AC128ACFUE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 27/42頁(yè)
文件大?。?/td> 0K
描述： MCU 8BIT 128K FLASH 64-QFP
標(biāo)準(zhǔn)包裝： 84
系列： MCF51AC
核心處理器： Coldfire V1
芯體尺寸： 32-位
速度： 50MHz
連通性： CAN，I²C，SCI，SPI
外圍設(shè)備： LVD，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 20x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-QFP
包裝： 托盤
Electrical Characteristics
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor
33
o
2.11
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
18
D Lock exit frequency tolerance 8
Dunl
4.47
—
5.97
%
19
D Lock time — FLL
tfll_lock
——
tfll_acquire+
1075(1/fint_t)
s
20
D Lock time — PLL
tpll_lock
——
tpll_acquire+
1075(1/fpll_ref)
s
21
D
Loss of external clock minimum frequency —
RANGE = 0
floc_low
(3/5)
f
int
—
kHz
1 Data in Typical column was characterized at 5.0 V, 25
C or is typical recommended value.
2 The resulting bus clock frequency must not exceed the maximum specified bus clock frequency of the device.
3 This specification applies when the FLL reference source or reference divider is changed, trim value changed or changing from
FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
4 This specification applies when the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
BUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
6 625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus
speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and
the sample point of a bit using 8 time quanta per bit.
7 Below D
lock minimum, the MCG enters lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already in
lock, then the MCG may stay in lock.
8 Below D
unl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
Table 16. MCG Frequency Specifications (continued)(Temperature Range = –40 to 105
C Ambient)
Num C
Rating
Symbol
Min
Typical1
Max
Unit
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