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參數(shù)資料
| 型號(hào)： | PCF51AC256BCPUE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 40/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 8BIT 256K FLASH 64-LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | MCF51AC |
| 核心處理器： | Coldfire V1 |
| 芯體尺寸： | 32-位 |
| 速度： | 50MHz |
| 連通性： | I²C，SCI，SPI |
| 外圍設(shè)備： | LVD，PWM，WDT |
| 輸入/輸出數(shù)： | 54 |
| 程序存儲(chǔ)器容量： | 256KB（256K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 20x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
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MCF51AC256 Family Configurations
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.7
Freescale Semiconductor
7
1.3.1
Feature List
32-bit Version 1 ColdFire central processor unit (CPU)
— Up to 50.33 MHz at 2.7 V – 5.5 V
— Provide 0.94 Dhrystone 2.1 DMIPS per MHz performance when running from internal RAM
(0.76 DMIPS per MHz when running from flash)
— Implements instruction set revision C (ISA_C)
On-chip memory
— Up to 256 KB flash memory read/program/erase over full operating voltage and temperature
— Up to 32 KB static random access memory (SRAM)
— Security circuitry to prevent unauthorized access to SRAM and flash contents
Power-Saving Modes
— Three low-power stop plus wait modes
— Peripheral clock enable register can disable clocks to unused modules, reducing currents;
allows clocks to remain enabled to specific peripherals in stop3 mode
System protection features
— Watchdog computer operating properly (COP) reset with options to run from independent LPO
clock or bus clock
— Low-voltage detection with reset or interrupt
— Illegal opcode and illegal address detection with programmable reset or exception response
— Flash block protection
Debug support
— Single-wire background debug interface
— Real-time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that
can be configured into a 1- or 2-level trigger
— On-chip trace buffer provides programmable start/stop recording conditions plus support for
continuous or PC-profiling modes
— Support for real-time program (and optional partial data) trace using the debug visibility bus
V1 ColdFire interrupt controller (CF1_INTC)
— Support of 40 peripheral I/O interrupt requests plus seven software (one per level) interrupt
requests
— Fixed association between interrupt request source and level plus priority, up to two requests
can be remapped to the highest maskable level + priority
— Unique vector number for each interrupt source
— Support for service routine interrupt acknowledge (software IACK) read cycles for improved
system performance
Multipurpose clock generator (MCG)
— Oscillator (XOSC); loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25
kHz to 38.4 kHz or 1 MHz to 16 MHz
— LPO clock as an optional independent clock source for COP and RTI
— FLL/PLL controlled by internal or external reference
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