參數(shù)資料
型號(hào): PCF85176T
廠商: NXP SEMICONDUCTORS
元件分類: 顯示驅(qū)動(dòng)器
英文描述: Universal LCD driver for low multiplex rates
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, PDSO56
封裝: 6.10 MM, PLASTIC, MO-153, SOT364-1, TSSOP-56
文件頁(yè)數(shù): 33/47頁(yè)
文件大?。?/td> 405K
代理商: PCF85176T
PCF85176
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 27 June 2011
33 of 47
NXP Semiconductors
PCF85176
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
[1]
Typical output duty factor: 50 % measured at the CLK output pin.
[2]
Not tested in production.
[3]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
IL
and V
IH
with an
input voltage swing of V
SS
to V
DD
.
Table 19.
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; V
LCD
= 2.5 V to 6.5 V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol
Parameter
Clock
f
clk(int)
internal clock frequency
f
clk(ext)
external clock frequency
f
fr
frame frequency
Dynamic characteristics
Conditions
Min
Typ
Max
Unit
[1]
1440
960
60
40
60
60
1970
-
82
-
-
-
2640
2640
110
110
-
-
Hz
Hz
Hz
Hz
s
s
internal clock
external clock
t
clk(H)
t
clk(L)
Synchronization
t
PD(SYNC_N)
t
SYNC_NL
t
PD(drv)
I
2
C-bus
[3]
Pin SCL
f
SCL
t
LOW
t
HIGH
Pin SDA
t
SU;DAT
t
HD;DAT
Pins SCL and SDA
t
BUF
HIGH-level clock time
LOW-level clock time
SYNC propagation delay
SYNC LOW time
driver propagation delay
-
1
-
30
-
-
-
-
30
ns
s
s
V
LCD
= 5 V
[2]
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
-
1.3
0.6
-
-
-
400
-
-
kHz
s
s
data set-up time
data hold time
100
0
-
-
-
-
ns
ns
bus free time between a STOP and
START condition
set-up time for STOP condition
hold time (repeated) START condition
set-up time for a repeated START
condition
rise time of both SDA and SCL signals
1.3
-
-
s
t
SU;STO
t
HD;STA
t
SU;STA
0.6
0.6
0.6
-
-
-
-
-
-
s
s
s
t
r
f
SCL
= 400 kHz
f
SCL
< 125 kHz
-
-
-
-
-
-
-
-
-
-
0.3
1.0
0.3
400
50
s
s
s
pF
ns
t
f
C
b
t
w(spike)
fall time of both SDA and SCL signals
capacitive load for each bus line
spike pulse width
on the I
2
C-bus
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