Remote 8-bit I/O expander for I2
參數(shù)資料
型號: PCF8574TS/3,112
廠商: NXP Semiconductors
文件頁數(shù): 23/24頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 20SSOP
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 75
接口: I²C
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時鐘: 100kHz
電源電壓: 2.5 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-LSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 管件
包括: POR
產(chǎn)品目錄頁面: 827 (CN2011-ZH PDF)
配用: 568-3615-ND - DEMO BOARD I2C
其它名稱: 568-3988-5
935275672112
PCF8574TDK
PCF8574TDK-ND
2002 Nov 22
8
Philips Semiconductors
Product specication
Remote 8-bit I/O expander for I2C-bus
PCF8574
6.4
Acknowledge
The number of data bytes transferred between the start
and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit (see Fig.8). The acknowledge bit is a
HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock
pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse, set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a stop condition.
Fig.8 Acknowledgment on the I2C-bus.
handbook, full pagewidth
MBC602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
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