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| 型號： | PCF8832 |
| 英文描述： | STN RGB - 384 output column driver |
| 中文描述： | 超扭曲的RGB - 384列驅(qū)動器輸出 |
| 文件頁數(shù)： | 46/76頁 |
| 文件大小： | 385K |
| 代理商： | PCF8832 |
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2002 Aug 16
46
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
12 I
2
C-BUS INTERFACE
12.1
Characteristics of the I
2
C-bus (Hs-mode)
The I
2
C-bus Hs-mode is for bi-directional, two-line
communication between different ICs or modules with
speeds up to 3.4 MHz. The only difference between
Hs-mode slave devices and F/S-mode slave devices is the
speed at which they operate, therefore the buffers on the
SCL and SDA outputs have an open drain. This is the
same for I
2
C-bus master devices which have an
open-drain SDA output and a combination of open-drain
pull-down and current source pull-up circuits on the SCL
output. Only the current source of one master is enabled
at any one time, and only during Hs-mode. Both lines must
be connected to a positive supply via a pull-up resistor.
Data transfer may be initiated only when the bus is not
busy.
12.1.1
S
YSTEM CONFIGURATION
Definitions of terms used:
Transmitter: the device which sends the data to the bus
Receiver: the device which receives the data from the
bus
Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronization: procedure to synchronize the clock
signals of two or more devices.
MGA807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig.46 System configuration.
12.1.2
B
IT TRANSFER
One data bit is transferred during each clock pulse (see Fig.47). The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
handbook, full pagewidth
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.47 Bit transfer.
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