參數(shù)資料
型號(hào)： PCF8832
英文描述： STN RGB - 384 output column driver
中文描述： 超扭曲的RGB - 384列驅(qū)動(dòng)器輸出
文件頁(yè)數(shù)： 7/76頁(yè)
文件大?。?/td> 385K
代理商： PCF8832
2002 Aug 16
7
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
7
FUNCTIONAL DESCRIPTION
7.1
I/O buffer and interface
The interface is the connection between the outside world
and PCF8832. One of five industrial standard interfaces
can be selected using the interface configuration inputs
PS2, PS1 and PS0.
7.2
Configuration control
It is possible to configure the PCF8832s to use external
voltages, see Table 2.
Table 1
Default configuration settings
Table 2
Analog circuit configuration
7.3
Oscillator
The on-chip oscillator provides the clock signal for the
display system. An external clock signal, if used, is
connected to the OSC input. In this case the internal
oscillator must be switched off by a software command.
To improve the timing accuracy there is an external
resistor option. If this option is used, the external resistor
must be connected between OSC and V
DD1
and the
appropriate register must be set. If the internal resistor is
selected, the OSC input must be left open-circuit.
7.4
Display data RAM
The Display Data RAM (DDRAM) is a 128
×
9
×
168-bit
static RAM for display data storage. During RAM access,
data is transferred to the DDRAM via the interface.
7.5
Address counter
The address counter sets the addresses of the display
data RAM for writing operations.
7.6
Display address counter
The display is generated by continuously reading-out rows
of RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set via the interface.
7.7
Command decoder
The command decoder identifies command words arriving
at the interface and routes the following data bytes to their
destination.
7.8
DC-to-DC converter
The voltage multiplier generates the required column
voltage V
COL
. Pins CA1 and CA2 must be connected to an
external capacitor. If the capacitive DC-to-DC converter is
switched off by AOFF = 1, then V
COL
must be supplied
externally.
7.9
LCD power supply
The LCD power supply block generates the row voltage
V
2
level V
M
(equivalent to
). If the LCD power supply is
switched off by AOFF = 1, then V
M
must be supplied from
an external source.
7.10
Internal reset
The internal reset circuit handles hardware and software
resets, provides the reset signal required internally and
controls the reset signal for the row driver IC.
7.11
Timing generator
The timing generator produces the various signals
required to coordinate the column driver with the row
driver.
7.12
Row driver control
The row driver IC is controlled completely by commands
from the column driver.
7.13
Column drivers and data latches
The LCD drive section includes 128
×
3 column outputs
(C0 to C383) which should be connected directly to the
LCD. The column output signals are generated in
accordance with the data in the display latches. The data
are loaded from the display RAM when the corresponding
row signal is active. Unused column outputs should be left
open-circuit when less than 384 columns are required.
INPUT
DEFAULT VALUE
CSCD
FSYN
LPOS
0
0
1
ANALOG SWITCHING0
EFFECT
AOFF = 0
AOFF = 1
analog part active
analog part switched off,
analog voltages are input
through V
COL
, V
M
------------
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