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xii
Table
65
66
67
71
72
73
74
75
76
77
78
79
710
711
712
713
714
715
716
717
718
719
720
721
722
81
82
83
84
85
86
87
88
89
810
811
812
813
814
815
816
817
818
Title
Page
66
67
68
71
73
74
75
75
76
76
77
78
79
79
710
710
711
712
713
713
714
715
716
717
718
81
84
85
86
87
88
89
811
811
812
813
815
816
817
818
820
822
824
Socket Force Event Register Description
Socket Control Register Description
Socket Power Management Register Description
Function 2 Configuration Register Map
Command Register Description
Status Register Description
Class Code and Revision ID Register Description
Latency Timer and Class Cache Line Size Register Description
Header Type and BIST Register Description
OHCI Base Address Register Description
TI Base Address Register Description
Subsystem Identification Register Description
Interrupt Line Register Description
PCI Interrupt Pin Register—Read-Only INTPIN Per Function
Minimum Grant and Maximum Latency Register Description
OHCI Control Register Description
Capability ID and Next Item Pointer Registers Description
Power Management Capabilities Register Description
Power Management Control and Status Register Description
Power Management Extension Registers Description
PCI PHY Control Register Description
PCI Miscellaneous Configuration Register Description
Link Enhancement Control Register Description
Subsystem Access Register Description
General-Purpose Input/Output Control Register Description
OHCI Register Map
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OHCI Version Register Description
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GUID ROM Register Description
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Asynchronous Transmit Retries Register Description
CSR Control Register Description
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Configuration ROM Header Register Description
Bus Options Register Description
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Configuration ROM Mapping Register Description
Posted Write Address Low Register Description
Posted Write Address High Register Description
Host Controller Control Register Description
Self-ID Count Register Description
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Isochronous Receive Channel Mask High Register Description
Isochronous Receive Channel Mask Low Register Description
Interrupt Event Register Description
Interrupt Mask Register Description
Isochronous Transmit Interrupt Event Register Description
Isochronous Receive Interrupt Event Register Description
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