參數(shù)資料
型號: PCI4515
廠商: Texas Instruments, Inc.
英文描述: SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED
中文描述: 單插槽CardBus控制器,它集成
文件頁數(shù): 36/216頁
文件大?。?/td> 1138K
代理商: PCI4515
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218
Table 214. CardBus PC Card Interface Control Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
A_CAUDIO
B12
I
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The controller
supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
A_CBLOCK
H15
I/O
CardBus lock. CBLOCK is used to gain exclusive access to a target.
A_CCD1
A_CCD2
N15
B11
I
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2
to identify card insertion and interrogate cards to determine the operating voltage and card type.
A_CDEVSEL
F19
I/O
CardBus device select. The controller asserts CDEVSEL to claim a CardBus cycle as the target device.
As a CardBus initiator on the bus, the controller monitors CDEVSEL until a target responds. If no target
responds before timeout occurs, then the controller terminates the cycle with an initiator abort.
A_CFRAME
E19
I/O
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When
CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
A_CGNT
G17
O
CardBus bus grant. CGNT is driven by the controller to grant a CardBus PC Card access to the CardBus
bus after the current data transaction has been completed.
A_CINT
E12
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.
A_CIRDY
F17
I/O
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
A_CPERR
G19
I/O
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following the data cycle during which a parity error is detected.
A_CREQ
C14
I
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus
bus as an initiator.
A_CSERR
C12
I
CardBus system error. CSERR reports address parity errors and other system errors that could lead to
catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup;
deassertion may take several CCLK periods. The controller can report CSERR to the system by assertion
of SERR on the PCI interface.
A_CSTOP
G18
I/O
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus
transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do
not support burst data transfers.
A_CSTSCHG
A12
I
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as a
wake-up mechanism.
A_CTRDY
G15
I/O
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and
CTRDY are asserted; until this time, wait states are inserted.
A_CVS1
A_CVS2
A13
B16
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with
CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.
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