參數(shù)資料
型號: PCM1601Y
英文描述: 24-Bit, 96kHz Sampling, 6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位,96kHz采樣,6通道,增強的多級,Δ-Σ數(shù)字模擬轉換器
文件頁數(shù): 18/28頁
文件大小: 253K
代理商: PCM1601Y
18
PCM1600, PCM1601
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
INZD
Infinite Zero Detect Mute Control
This bit is Read/Write.
Default Value: 0
INZD = 0
INZD = 1
Infinite Zero Detect Mute Disabled (default)
Infinite Zero Detect Mute Enabled
The INZD bit is used to enable or disable the Zero Detect Mute function described in the Zero Flag and Infinite
Zero Detect Mute section in this data sheet. The Zero Detect Mute function is independent of the Zero Flag
output operation, so enabling or disabling the INZD bit has no effect on the Zero Flag outputs (ZERO1-ZERO6,
ZEROA).
DACx
DAC Operation Control
where x = 1-6, corresponding to the DAC output V
OUT
x.
These bits are Read/Write.
Default Value: 0
DACx = 0
DACx = 1
DAC Operation Enabled (default)
DAC Operation Disabled
The DAC operation controls are used to enable and disable the DAC outputs, V
OUT
1 through V
OUT
6. When
DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier
input is switched to the DC common-mode voltage (V
COM
1 or V
COM
2), equal to V
CC
/2.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 8
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
INZD
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
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相關代理商/技術參數(shù)
參數(shù)描述
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