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參數(shù)資料
| 型號： | PCM1602APTR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 6/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 24BIT 6CH 192KHZ 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 6 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 240mW |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 6 電壓，單極 |
| 采樣率（每秒）： | 192k |
| 配用： | DEM-DAI1602-ND - EVAL FIXTURE FOR PCM1602 |
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Reset
Reset Removal
VDD
2.4 V
2 V
1.6 V
Internal Reset
System Clock
T0014-08
0 V
Don’t Care
1024 System Clocks
Reset Removal
1024 System Clocks
RST
Internal Reset
System Clock
Reset
T0015-06
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
www.ti.com
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1602A includes a power-on-reset function, as shown in Figure 20. With the system clock active, and
VDD > 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires
1024 system clocks from the time VDD > 2 V. After the initialization period, the PCM1602A is set to its reset
default state, as described in the Mode Control Registers section of this data sheet.
The PCM1602A also includes an external reset capability using the RST input (pin 37). This allows an external
controller or master reset circuit to force the PCM1602A to initialize to its reset default state. For normal
operation, RST should be set to a logic-1.
The external reset operation and timing is shown in Figure 21. The RST pin is set to logic-0 for a minimum of
20 ns. After the initialization sequence is completed, the PCM1602A is set to its reset default state, as described
in the Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level (or VCC/2).
After the reset period, the internal registers are initialized in the next 1/fS period and, if SCKI, BCK, and LRCK
are provided continuously, the PCM1602A provides proper analog output with the group delay time given in the
Electrical Characteristics section of this data sheet.
The external reset is especially useful in applications where there is a delay between PCM1602A power-up and
system-clock activation. In this case, the RST pin should be held at a logic-0 level until the system clock has
been activated.
Figure 20. Power-On-Reset Timing
Figure 21. External Reset Timing
14
Copyright 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): PCM1602A
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