參數(shù)資料
型號： PCM1602APTR
廠商： Texas Instruments
文件頁數(shù)： 7/46頁
文件大?。?/td> 0K
描述： IC DAC 24BIT 6CH 192KHZ 48-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 6
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 240mW
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 6 電壓，單極
采樣率（每秒）： 192k
配用： DEM-DAI1602-ND - EVAL FIXTURE FOR PCM1602
www.ti.com
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1602A consists of a 5-wire synchronous serial port. It includes LRCK (pin
41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), and DATA3 (pin 47). BCK is the serial audio bit clock, and is
used to clock the serial data present on DATA1, DATA2, and DATA3 into the audio interface serial shift register.
Serial data is clocked into the PCM1602A on the rising edge of BCK. LRCK is the serial audio left/right clock. It is
used to latch serial data into the serial audio interface internal registers.
Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK
be derived from the system clock input, SCKI. LRCK is operated at the sampling frequency (fS). BCK can be
operated at 32, 48, or 64 times the sampling frequency (I2S format does not support BCK = 32 fS).
Internal operation of the PCM1602A is synchronized with LRCK. Accordingly, internal operation of the device is
suspended when the sampling rate clock (LRCK) is changed, or when SCKI and/or BCK is interrupted at least for
a 3-bit clock cycle. If SCKI, BCK, and LRCK are provided continuously after this suspended state, the internal
operation is resynchronized automatically within a period of less than 3/fS. During this resynchronization period
and for a 3/fS time thereafter, the analog outputs are forced to the bipolar zero level, VCC/2. External resetting is
not required.
AUDIO DATA FORMATS AND TIMING
The PCM1602A supports industry-standard audio data formats, including standard, I2S, and left-justified (see
Figure 22). Data formats are selected using the format bits, FMT[2:0], in register 9. The default data format is
24-bit standard. All formats require binary 2s complement, MSB-first audio data. See Figure 23 for a detailed
timing diagram of the serial audio interface.
DATA1, DATA2, and DATA3 each carry two audio channels, designated as the left and right channels. The
left-channel data always precedes the right-channel data in the serial data stream for all data formats. Table 2
shows the mapping of the digital input data to the analog output pins.
Copyright 2005–2010, Texas Instruments Incorporated
15
Product Folder Link(s): PCM1602A
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