參數(shù)資料
型號: PCM1796DB
元件分類: DAC
英文描述: 24BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
中文描述: 24位192千赫采樣高級分段音頻立體聲數(shù)模轉(zhuǎn)換器
文件頁數(shù): 25/57頁
文件大?。?/td> 512K
代理商: PCM1796DB
SLES100 DECEMBER 2003
www.ti.com
25
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The PCM1796 includes a number of user-programmable functions which are accessed via mode control registers.
The registers are programmed using the serial control interface, which is previously discussed in the
SPI Interface
and
I
2
C INTERFACE
sections of this data sheet. Table 3 lists the available mode-control functions, along with their
default reset conditions and associated register index.
Table 3. User-Programmable Function Controls
FUNCTION
DEFAULT
REGISTER
BIT
PCM
DSD
DF
BYPASS
Digital attenuation control
0 dB to –120 dB and mute, 0.5 dB step
Attenuation load control
Disabled, enabled
0 dB
Register 16
Register 17
Register 18
ATL[7:0] (for L-ch)
ATR[7:0] (for R-ch)
ATLD
yes
Attenuation disabled
yes
Input audio data format selection
16-, 20-, 24-bit standard (right-justified) format
24-bit MSB-first left-justified format
16-/24-bit I2S format
Sampling rate selection for de-emphasis
Disabled,44.1 kHz, 48 kHz, 32 kHz
24-bit I2S format
Register 18
FMT[2:0]
yes
yes
De-emphasis disabled
Register 18
DMF[1:0]
yes
yes(1)
De-emphasis control
Disabled, enabled
Soft mute control
Soft mute disabled, enabled
De-emphasis disabled
Register 18
DME
yes
Mute disabled
Register 18
MUTE
yes
Output phase reversal
Normal, reverse
Normal
Register 19
REV
yes
yes
yes
Attenuation speed selection
×
1fS,
×
(1/2)fS,
×
(1/4)fS,
×
(1/8)fS
DAC operation control
Enabled, disabled
×
1 fS
Register 19
ATS[1:0]
yes
DAC operation enabled
Register 19
OPE
yes
yes
yes
Stereo DF bypass mode select
Monaural, stereo
Digital filter rolloff selection
Sharp rolloff, slow rolloff
Monaural
Register 19
DFMS
yes
Sharp rolloff
Register 19
FLT
yes
Infinite zero mute control
Disabled, enabled
System reset control
Reset operation , normal operation
Disabled
Register 19
INZD
yes
yes
Normal operation
Register 20
SRST
yes
yes
yes
DSD interface mode control
DSD enabled, disabled
Digital-filter bypass control
DF enabled, DF bypass
Disabled
Register 20
DSD
yes
yes
DF enabled
Register 20
DFTH
yes
yes
Monaural mode selection
Stereo, monaural
Channel selection for monaural mode data
L-channel, R-channel
Stereo
Register 20
MONO
yes
yes
yes
L-channel
Register 20
CHSL
yes
yes
yes
Delta-sigma oversampling rate selection
×
64 fS,
×
128 fS,
×
32 fS
PCM zero output enable
DSD zero output enable
FUNCTION AVAILABLE ONLY FOR READ
Zero detection flag
Not zero, zero detected
×
64 fS
Register 20
OS[1:0]
yes
yes(2)
yes
Enabled
Disabled
Register 21
Register 21
PCMZ
DZ[1:0]
yes
yes
yes
Not zero = 0
Zero detected = 1
Register 22
ZFGL (for L-ch)
ZFGR (for R-ch)
yes
yes
yes
Device ID (at TDMCA)
(1)When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.
(2)When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.
Register 23
ID[4:0]
yes
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