參數(shù)資料
型號: PCM1796DB
元件分類: DAC
英文描述: 24BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
中文描述: 24位192千赫采樣高級分段音頻立體聲數(shù)模轉(zhuǎn)換器
文件頁數(shù): 39/57頁
文件大?。?/td> 512K
代理商: PCM1796DB
SLES100 DECEMBER 2003
www.ti.com
39
Audio Format
The PCM1796 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit,
and 24-bit audio data, as shown in Figure 40. The audio format is selected by the FMT[2:0] bits of control register18.
MSB
LSB
16
BCK
DATA,
DATAL, DATAR
1/4 fS or 1/8 fS
WDCK
Audio Data Word = 16-Bit
Audio Data Word = 20-Bit
DATA,
DATAL, DATAR
Audio Data Word = 24-Bit
DATA,
DATAL, DATAR
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
16
15
MSB
LSB
16
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
20
19
20
17 18 19
MSB
LSB
16
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
24
23
20
17 18 19
24
21 22 23
Figure 40. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
System Clock (SCK) and Interface Timing
The PCM1796 in an application using an external digital filter requires the synchronization of WDCK and the system
clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATA, DATAL,
and DATAR is shown in Figure 41.
DATA
DATAL
DATAR
t(BCH)
BCK
WDCK
t(BCL)
t(LB)
t(BCY)
t(DS)
t(DH)
1.4 V
1.4 V
t(BL)
1.4 V
PARAMETER
MIN
20
MAX
UNITS
ns
t(BCY)
t(BCL)
t(BCH)
t(BL)
t(LB)
t(DS)
t(DH)
BCK pulse cycle time
BCK pulse duration, LOW
7
ns
BCK pulse duration, HIGH
7
ns
BCK rising edge to WDCK falling edge
5
ns
WDCK falling edge to BCK rising edge
5
ns
DATA, DATAL, DATAR setup time
5
ns
DATA, DATAL, DATAR hold time
5
ns
Figure 41. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
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相關代理商/技術參數(shù)
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