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Audio Serial Interface
Audio Data Formats and Timing
The PCM3793A/94A supports I
2
S, right-justified, left-justified, and DSP formats. The data formats are shown in
Figure 29
and are selected using registers 70 and 81 (RFM[1:0], PFM[1:0]). All formats require binary
2s-complement, MSB-first audio data. The default format is I
2
S.
Figure 27
shows a detailed timing diagram.
PCM3793A
PCM3794A
SLAS529A–JANUARY 2007–REVISED FEBRUARY 2007
Table 5. Power Consumption Table
OPERATION MODE
POWER SUPPLY CURRENT [mA]
PD [mW]
PD [mW]
V
(1.8 V)
V
(3.3 V)
V
(3.3 V)
V
(3.3 V)
V
TOTAL
(V
DD
= 1.8
V)
TOTAL
(V
DD
= 3.3 V)
(3.3 V)
All Power Down
0
0
0.007
0.002
0
0.03
0.03
All Active
2.5
5.1
7.5
11.6
0.1
67.7
80.2
PLAYBACK WITH DIGITAL INPUT
Line output and headphone output
1.18
2.51
1.79
0.54
0.09
10.1
16.3
Headphone output with sound effect
1.81
3.84
1.79
0.54
0.09
11.2
20.7
Capless headphone output
1.18
2.51
1.8
0.75
0.09
10.8
17.0
Headphone output with line input (AIN2L/AIN2R)
1.18
2.52
2.09
0.54
0.09
11.1
17.3
Headphone output with mono microphone input (AIN1L, 20 dB)
1.18
2.52
2.5
0.54
0.09
12.5
18.6
Headphone output with mono differential microphone input
(AIN1L/AIN1R, 20 dB)
1.18
2.52
2.8
0.54
0.09
13.4
19.6
Stereo speaker output
1.21
2.58
2.18
10.94
0.09
45.8
52.1
Mono speaker output
1.2
2.57
2.01
5.61
0.09
27.6
33.9
Speaker output with line input (AIN2L/AIN2R)
1.21
2.57
2.48
10.95
0.09
46.8
53.1
Speaker output with mono microphone input (AIN1L, 20 dB)
1.21
2.58
2.89
10.96
0.09
48.2
54.5
Speaker output with mono differential microphone input
(AIN1L/AIN1R, 20 dB)
1.2
2.58
3.2
10.98
0.09
49.3
55.6
PLAYBACK WITHOUT DIGITAL INPUT
Line input (AIN2L/AIN2R) to headphone output
0
0
0.76
0.53
0
4.3
4.3
Mono line input (AIN2L) to headphone output
0
0
0.61
0.53
0
3.8
3.8
Mono microphone Input (AIN1L, 20 dB) to headphone output
0
0
1.18
0.53
0
5.6
5.6
Mono differential microphone input (AIN1L/AIN1R, 20 dB) to
headphone output
0
0
1.48
0.53
0
6.6
6.6
Mono microphone input (AIN1L, 20 dB) to speaker output
0
0
1.57
10.92
0
41.2
41.2
RECORDING
Line input (AIN3L/AIN3R)
1.86
3.89
4.58
0.13
0.1
19.1
28.7
Microphone input (AIN1L/AIN1R, 20 dB)
1.86
3.91
5.14
0.13
0.1
21.1
30.6
Microphone input (AIN1L/AIN1R, 20 dB) with ALC
2.78
5.77
5.14
0.13
0.1
22.7
36.8
Mono microphone input (AIN1L, 20 dB)
1.4
2.93
3.6
0.13
0.1
15.2
22.3
Mono microphone input (AIN1L, 20 dB) with ALC
2.2
4.74
3.6
0.13
0.1
16.6
28.3
Mono differential microphone input (AIN1L/AIN1R, 20 dB)
1.4
2.94
3.96
0.13
0.1
16.3
23.5
Mono differential microphone input (AIN1L/AIN1R, 20 dB) with
ALC
2.2
4.74
3.96
0.13
0.1
17.8
29.5
Conditions:
48 kHz/256 f
S
, 16 bits, slave mode, zero data input, no load
The audio serial interface for the PCM3793A/94A comprises LRCK, BCK, DIN, and DOUT. Sampling rate (f
S
),
left and right channel are present on LRCK. DIN receives the serial data for the DAC interpolation filter, and
DOUT transmits the serial data from the ADC decimation filter. BCK clocks the transfer of serial audio data on
DIN and DOUT in its high-to-low transition. BCK and LRCK should be synchronized with audio system clock.
Ideally, it is recommended that they be derived from it.
The PCM3793A/94A requires LRCK to be synchronized with the system clock. The PCM3793A/94A does not
require a specific phase relationship between LRCK and the system clock.
The PCM3793A/94A has both master mode and slave mode interface formats, which can be selected by
register 84 (MSTR). In master mode, the PCM3793A/94A generates LRCK and BCK from the system clock.
23
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