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參數(shù)資料
| 型號： | PCM4222_07 |
| 英文描述： | High-Performance, Two-Channel, 24-Bit, 216kHz Sampling Multi-Bit Delta-Sigma Analog-to-Digital Converter |
| 中文描述： | 高性能，雙通道，24位，216kHz的采樣多位Δ-Σ模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 609K |
| 代理商： | PCM4222_07 |
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PCM OUTPUT WORD LENGTH REDUCTION
The PCM4222 is typically configured to output 24-bit linear PCM audio data. However, internal word length
reduction circuitry may be utilized to reduce the 24-bit data to 20-, 18-, or 16-bit data. This reduction is
accomplished by using a Triangular PDF dithering function. The OWL0 (pin 42) and OWL1 (pin 41) inputs are
utilized to select the output data word length.
Table 7
summarizes the output word length configuration options.
OVERFLOW INDICATORS
The PCM4222 includes two active-high digital overflow outputs, OVFL (pin 37) and OVFR (pin 38),
corresponding to the left and right channels, respectively. These outputs are functional when the PCM output
mode is enabled, as the overflow detection circuitry is incorporated into the digital filter engine. The overflow
indicators are forced high whenever a digital overflow is detected for a given channel. The overflow indicators
may be utilized as clipping flags, and monitored using a host processor or light-emitting diode (LED) indicators.
When driving a LED, the overflow output may be buffered to ensure adequate drive for the LED. A
recommended buffer is Texas Instruments'
SN74LVC1G125
. Equivalent buffers may be substituted
DIRECT STREAM DIGITAL (DSD) OUTPUT OPERATION
The PCM4222 supports 1-bit, direct stream digital (DSD) output data. The DSD data stream is utilized as the
format for super audio CD (SACD) data. An on-chip DSD engine converts the multi-bit delta-sigma modulator
output data to 1-bit DSD output data.
Figure 46
shows a simplified functional block diagram for this process. The
PCM4222 allows for the simultaneous output of both PCM and DSD output data, enabling both data types to be
captured for recording and editing purposes.
PCM4222
SBAS399A–OCTOBER 2006–REVISED MARCH 2007
Table 6. Digital High-Pass Filter Configuration
HPFDR (pin 17) or HPFDL (pin 18)
LO
HI
HIGH-PASS FILTER STATE
Enabled for the corresponding channel
Disabled for the corresponding channel
Table 7. PCM Audio Data Word Length Selection
OWL1 (pin 41)
LO
LO
HI
HI
OWL0 (pin 42)
LO
HI
LO
HI
OUTPUT WORD LENGTH
24 bits
18 bits
20 bits
16 bits
The DSD engine operates in a Master mode configuration, with one data clock output and two data outputs,
corresponding to the left and right channels, respectively. The DSDCLK output (pin 27) functions as the DSD
data or bit clock and operates at the output data rate, which is typically set to either 64x or 128x the base rate of
44.1kHz. This configuration results in an output data rate of either 2.8224MHz or 5.6448MHz. The 2.8224MHz is
the standard playback rate for SACD, while the 128x rate may be desirable for recording or processing
purposes. The DSDL (pin 28) and DSDR (pin 29) outputs are utilized for the left and right channel data,
respectively.
The DSD output mode is enabled using the DSDEN input (pin 22).
Table 8
summarizes the function of this pin.
The DSD output rate is selected using the DSDMODE input (pin 24).
Table 9
summarizes the operation of this
pin.
Table 8. DSD Output Configuration
DSDEN (pin 22)
LO
HI
DSD OUTPUT MODE
DSD Output Mode is disabled with clock and data outputs forced low
DSD Output Mode is enabled
25
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| PCM4222EVM | 功能描述:音頻 IC 開發(fā)工具 PCM4222 Evaluation Module RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| PCM4222EVM | 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL |
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| PCM4222PFBR | 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC 24-Bit/216kHz 124dB RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
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