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參數(shù)資料
| 型號(hào)： | PCSYSCON |
| 英文描述： | PC(ISA)BUS I/O CARD |
| 中文描述： | 電腦（ISA）總線的I / O卡 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 383K |
| 代理商： | PCSYSCON |
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All of these signals except for WIDS are available in inverted form on
the 50-way connector Pl2. WDIS is replaced by an inverted version
of the buzzer signal.
Watchdog Registers
Two registers control operation of the watchdog. The STARTW
register at pointer register 9 (write) starts the watchdog with either a
two or a ten second timeout period. Only one bit (bit 0) has any
meaning in the STARTW register. If this is a 1 the longer timeout
period is selected. If it is 0 the shorter period is selected.
The RETRIGW register at pointer value 8 (write) must be written to
in order to prevent the watchdog timing out. Any value may be
written. Once the watchdog has started it cannot be stopped. This is
because otherwise software that had crashed could have activated
the routine that stopped the watchdog, thus removing the protection.
The WDIS bit in the STATUS register is a 1 until the watchdog has
been started.
It is recommended that your watchdog retriggering routine has the
following characteristics:
It is not callable routine or function, but is in-line code in the main
program loop
It is not triggered by an interrupt
It is executed once in the main program loop
2192-09065-000-000
Section 2. The PCSYSCON I/O Map
Page 13
J278 PCSYSCON
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