參數(shù)資料
型號: PDIUSBD12D
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: nullUSB interface device with parallel bus
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO28
封裝: 7.50 MM , PLASTIC, MS-013, SOT-136-1, SOP-28
文件頁數(shù): 13/35頁
文件大?。?/td> 838K
代理商: PDIUSBD12D
Philips Semiconductors
PDIUSBD12
USB interface device with parallel bus
Product data
Rev. 08 — 20 December 2001
13 of 35
9397 750 09238
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Table 5:
Bit
7 to 6
Set mode command, Configuration byte: bit allocation
Symbol
Description
ENDPOINT
CONFIGURAT
ION
mode 1 (ISO-OUT mode)
mode 2 (ISO-IN mode)
mode 3 (ISO-I/O mode)
See
Section 8 “Endpoint description”
for more details.
SoftConnect
A ‘1’ indicates that the upstream pull-up resistor will be connected
if V
BUS
is available. A ‘0’ means that the upstream resistor will not
be connected. The programmed value will not be changed by a
bus reset.
INTERRUPT
MODE
generate an interrupt. A ‘0’ indicates that only OK is reported. The
programmed value will not be changed by a bus reset.
CLOCK
RUNNING
even during Suspend state. A ‘0’ indicates that the internal clock,
crystal oscillator and PLL are stopped whenever not needed. To
meet the strict Suspend current requirement, this bit needs to be
set to ‘0’. The programmed value will not be changed by a bus
reset.
NO
LAZYCLOCK
indicates that the CLKOUT switches to LazyClock 1ms after the
Suspend pin goes HIGH. LazyClock frequency is 30 kHz
±
40%.
The programmed value will not be changed by a bus reset.
These two bits set the endpoint configurations as follows:
mode 0 (Non-ISO mode)
4
3
A ‘1’ indicates that all errors and “NAKing” are reported and will
2
A ‘1’ indicates that the internal clocks and PLL are always running
1
A ‘1’ indicates that CLKOUT will not switch to LazyClock. A ‘0’
See
Table 6
for bit allocation.
Fig 7.
Set mode command, Clock division factor byte.
7
0
6
0
5
X
4
X
3
1
2
0
1
1
1
0
POWER ON VALUE
CLOCK DIVISION FACTOR
RESERVED
SV00862
SET_TO_ONE
SOF-ONLY INTERRUPT MODE
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