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參數(shù)資料
| 型號(hào)： | PDSP1601ABOAC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 位片處理器 |
| 英文描述： | ALU and Barrel Shifter |
| 中文描述： | 16-BIT, BIT-SLICE MICROPROCESSOR, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 128K |
| 代理商： | PDSP1601ABOAC |
PDSP1601/PDSP1601A
8
The Register Files
There are two on-chip register files (ALU and Shifter), each
containing two 16 bit registers and each supporting 8
instructions (see Table 4). The instructions for the ALU
register file and the Barrel Shifter Register file are the same.
The Inputs to the register files come from either the ALU or
the Barrel Shifter, and are loaded into the Register files on the
rising edge of CLK.
The register file instructions are latched such that the
instruction will not start executing until the rising edge of the
CLK latches the instruction into the device.
The register file instructions (see Table 4) allow input data
to be loaded into either, neither or both of the registers. Data
is loaded at the end of the cycle in which the instruction is
executing.
The register file instructions allow the output to be sourced
from either of the two registers, the selected output will be valid
during the cycle in which the instruction is executing.
Operation
Load Left Reg Output Right Reg
Load Right Reg Output Left Reg
Load Left Register, Output Left Reg
Load Right Register, Output Right Reg
Load Both Registers, Output Left Reg
No Load Operation, Output Right Reg
No Load Operation, Output Left Reg
No Load Operation, Pass Barrel Shifter Result
Operation
Load Left Reg Output Right Reg
Load Right Reg Output Left Reg
Load Left Register, Output Left Reg
Load Right Register, Output Right Reg
Load Both Registers, Output Left Reg
No Load Operation, Output Right Reg
No Load Operation, Output Left Reg
No Load Operation, Pass ALU Result
Inst
0
1
2
3
4
5
6
7
RA2-RA0
000
001
010
011
100
101
110
111
Mnemonic
LLRRR
LRRLR
LLRLR
LRRRR
LBRLR
NOPRR
NOPLR
NOPPS
ALU REGISTER INSTRUCTIONS
Inst
0
1
2
3
4
5
6
7
RA2-RA0
000
001
010
011
100
101
110
111
Mnemonic
LLRRR
LRRLR
LLRLR
LRRRR
LBRLR
NOPRR
NOPLR
NOPPS
SHIFTER REGISTER INSTRUCTIONS
Table 4 ALU and shift register instructions mnemonics
MNEMONICS
LXXYY
LBOXX
NOPXX No Load Operation,
Load XX = Target,
Load Both Registers, XX
YY
= Source of Output
= Source of Output
= Source of Output
XX
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP1601AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| PDSP1601AC0/AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fixed Point ALU |
| PDSP1601ALC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| PDSP1601B0/AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fixed Point ALU |
| PDSP1601B0/LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fixed Point ALU |
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