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參數(shù)資料
| 型號(hào)： | PDSP16116MCGC1R |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 16 by 16 Bit Complex Multiplier |
| 中文描述： | 16-BIT, DSP-MULTIPLIER, CQFP144 |
| 封裝： | CERAMIC, QFP-144 |
| 文件頁(yè)數(shù)： | 17/18頁(yè) |
| 文件大?。?/td> | 157K |
| 代理商： | PDSP16116MCGC1R |
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PDSP16116/A/MC
17
Min.
5
5
5
5
5
11
-
11
-
14
-
14
-
14
-
-
-
-
-
-
100
30
20
-
-
Switching Characteristics
CLK rising edge to P-PORTS
CLK rising edge to WTOUT1:0
CLK rising edge to GWR4:0
CLK rising edge to SFTA1:0
CLK rising edge to SFTR2:0
Setup CEX or CEY to CLK rising edge
Hold CEX or CEY to CLK rising edge
Setup X or Y port inputs to CLK rising edge
Hold X or Y port inputs to CLK rising edge
Setup WTA1:0, WTB1:0,
SOBFP
or
EOPSS
inputs
to CLK rising edge
Hold WTA1:0, WTB1:0,
SOBFP
or
EOPSS
inputs to
CLK rising edge
Setup CONX or CONY inputs to CLK rising edge
Hold CONX or CONY inputs to CLK rising edge
Setup AR15:13 or AI15:13 to CLK rising edge
Hold AR15:13 or AI15:13 to CLK rising edge
OPSEL to valid P-PORTS
OER
or
OEI
rising PR-PORT or PI-PORT high to Z
OER
or
OEI
rising PR-PORT or PI-PORT low to Z
OER
or
OEI
falling PR-PORT or PI-PORT Z to high
OER
or
OEI
falling PR-PORT or PI-PORT Z to low
Clock period
Clock high time
Clock low time
Vcc Current (CMOS input levels)
Vcc Current (TTL input levels)
Min.
5
5
5
5
5
8
-
8
-
8
-
8
-
-
-
-
-
-
-
-
50
12
12
-
-
Max.
45
30
30
60
50
-
0
-
2
-
0
-
0
-
0
35
35
45
22
24
-
-
-
60
100
Max.
23
20
20
30
28
-
0
-
0
-
0
-
0
-
0
20
25
25
18
18
-
-
-
80
130
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
mA
mA
Conditions
PDSP16116A
PDSP16116
Characteristic
Units
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
see Fig.9
see Fig.9
see Fig.9
see Fig.9
see Note 4
see Note 4
NOTE 4 :- V
CC
= Max Outputs unloaded, clock freq = Max
Delay from output
high to output
high impedance
Test
Waveform - measurement level
Delay from output
low to output
high impedance
H
V
0.5V
V
0.5V
L
1.5V
0.5V
1.5V
0.5V
Delay from output
high impedance to
output low
Delay from output
high impedance to
output high
V - Voltage reached when output driven hig
V - Voltage reached when output driven low
Fig.10 Three state delay measurement load
V
T
= 0V
V
T
= Vcc
DUT
30pF
1.5K
VT
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PDSP16116MCGGDR | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:16 X 16 Bit Complex Multiplier |
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| PDSP16256/A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:I/Q Splitter/NCO |
| PDSP16256/BO/AC | 制造商:Microsemi Corporation 功能描述: |
| PDSP16256_98 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter |
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