參數(shù)資料
型號: PECL_RX_C3
廠商: AUSTRIAMICROSYSTEMS AG
英文描述: CMOS PECL Receiver
中文描述: PECL的接收機(jī)的CMOS
文件頁數(shù): 1/6頁
文件大小: 280K
代理商: PECL_RX_C3
RevisionB,10.09.02
Page1of6
ANALOG IP BLOCK
PECL_RX - CMOS PECL Receiver
DATA SHEET
FEATURES
!
PECL_RX area:0.1
mm
2
,
size:x
=
300
μ
m y
=
340
μ
m
PERXBIAS
size:x
=
382
μ
m y
=
375
μ
m
3.3
V ±10%supplyvoltage
622
Mb/stransmssionspeed
1
nsmax.propagationdelay
Powerdissipation23
mWat3.3
V staticwithout
PERXBIAS
Junctiontemperature–40
-
125°C
OutputlevelsfullycompatiblewithF100KPECL
Famly
Powerdownmode
!
!
!
!
!
!
!
!
DESCRIPTION
ThePECL_RX isa3.3
V PECLdifferentiallinereceiver
featuringanoperatingfrequencyupto311
MHz(622
Mb/s)
andacceptingstandardF100Klevels(referredtothepositive
supply).
ThePECL_RX accepts(750
mV)differentialinputsignalsand
translatesthemtoCMOS outputlevels.
Withthecompanionlinedriver(PECL_TX )itcanbeusedfor
highspeedapplications.
ThecellPECL_RX requiresthePERXBIAS cellforbiasing.
PERXBIAS candriveupto3PECL_RX cells.Anexternal
voltagereferencemustbeused.
ThePECL_RX canbesetinpowerdownmode.
PROCESS
C35B3(0.35um
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