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參數(shù)資料
| 型號： | PECL_RX |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 英文描述： | CMOS PECL Receiver |
| 中文描述： | PECL的接收機(jī)的CMOS |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 280K |
| 代理商： | PECL_RX |
Datasheet:PECL_RX - C35
RevisionB,10.09.02
Page4of6
SYMBOL OF PECL_RX
XPD
High
High
Low
VINP
High
Low
X
VINN
Low
High
X
VOUTP
High
Low
High
VOUTN
Low
High
Low
PINLIST OF PECL_RX
Pin
VDDPECL
Description
PositiveSupplyforPECL
Receiver
PositiveSupply
PositiveSupplyforCMOS
OutputBuffer
NegativeSupply
NegativeSupply
BiasCurrent
BiasCurrent
VoltageReference
PowerDown
TestPin
PositiveInput
NegativeInput
Pos.PECLOutput
Neg.PECLOutput
Type
Supply
VDDA
VDDCMOS
Supply
Supply
VSSPECL
VSSCMOS
IREFP
IREFN
VMID
XPD
SIM
VINP
VINN
VOUTP
VOUTN
Supply
Supply
Analog
Analog
Analog
Digital
Digital
Analog
Analog
Digital
Digital
SYMBOL OF PERXBIAS
PINLIST OF PERXBIAS
Pin
VDDA
VSSA
IREFP1
IREFP2
IREFP3
IREFN1
IREFN2
IREFN3
VMID
XSIM
VREF
Description
PositiveSupply
NegativeSupply
BiasCurrent
BiasCurrent
BiasCurrent
BiasCurrent
BiasCurrent
BiasCurrent
VoltageReference
TestPin
ExternalReference
Voltage
Type
Supply
Supply
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Digital
Analog
THEORY OF OPERATION
ThePECL_RX isadifferentiallinereceiverwhichacceptslow
voltageinputsignalsaccordingtoF100Kstandard.
Theinputsignallinesmustbe50
transmssionlines.Atthe
receiverinputeachsignalhastobetermnatedtothevoltagelevel
V
T
(whereV
T
=
VDDPECL
–
2
V)withanexternaltermnation
resistorof50
, butalsoothertermnationschemesarepossible.
ThecellPECL_RX canbesetinpowerdownmode.Itrequiresthe
PERXBIAS cellforbiasing.PERXBIAS candriveupto3
PECL_RX cells.Anexternalvoltagereferencemustbeused.
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