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參數(shù)資料
| 型號： | PECL |
| 英文描述： | LTC3203B, LTC3203-1, and LTC3203B-1 Evaluation Kits |
| 中文描述： | PECL的驅(qū)動器（188K的隨機讀寫） |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 188K |
| 代理商： | PECL |
AN-SETS-5
PECL Driver
ADVANCED COMMUNICATIONS
APPLICATION NOTE
Revision 2.0/August 2001 Semtech Corp.
Page 3
www.semtech.com
1
Introduction
This application note is intended to clarify some of the issues surrounding PECL drivers in a CMOS process. There has
been some concern because the output levels do not comply with the original bipolar specifications. This note will
explain the reasons for this and will propose some possible workarounds to allow interfacing to standard PECL input
stages.
2
The PECL Standard
The following are the standard PECL input and output levels.
3
Semtech CMOS Driver
These are the quoted drive levels for the PECL output stages used on the SETS chips. The max levels are set to the
same figures as for the PECL standard but it should be noted that in practice the actual max levels will be lower than
these figures.
The assumed termination is 50ohm to VDD-2V at a nominal VDD=3.3V. However this means that for VDD=3.6V the
termination voltage will be VDD-2.2V hence it is possible to get a min Vol level of VDD-2.1V
As can be seen, the output levels are generally lower than the PECL standard as formulated for the original PECL driver
designs implemented in BiPolar processes.
The reason for this is that the High level is achieved by switching the gate of an NMOS source follower to VDD. The
output High level is then determined by the threshold drop of the NMOS transistor. Since these are generally higher in
value than the threshold drop of a bipolar transistor this means that the resultant High level for a CMOS driver will be
lower than that of a Bipolar driver. Since the drive levels standards were originally set to accommodate the variation
range seen in Bipolar transistors this is the reason why the standard does not easily accommodate CMOS processes.
Since the Low levels are set by switching the NMOS driver gate to a level less than VDD, it would be possible to make
these comply with the Vol standard but since this would result in the signal amplitude being reduced,
it was decided to keep the amplitude at the same level and hence the output Low levels are also lower than the original
standard.
Table 2.1
PECL Input and Output Levels
Parameter
Symbol
Min
Max
Units
Driver High
Voh
VDD-1.02
VDD-0.88
V
Driver Low
Vol
VDD-1.81
VDD-1.62
V
Receiver High
Vih
VDD-1.16
VDD-0.88
V
Receiver Low
Vil
VDD-1.81
VDD-1.48
V
Table 3.1
Semtech CMOS Driver Levels
Parameter
Symbol
Min
Max
Units
Driver High
Voh
VDD-1.25
VDD-0.88
V
Driver Low
Vol
VDD-2.1
VDD-1.62
V
相關PDF資料 |
PDF描述 |
|---|---|
| PEEL153C-30 | Electrically-Erasable PLD |
| PEEL153C-35 | Voltage Comparator; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C |
| PEEL153C-40 | Voltage Comparator; Package: PDIP; No of Pins: 8; Temperature Range: 0°C to +70°C |
| PEEL153P-30 | Electrically-Erasable PLD |
| PEEL153P-35 | Electrically-Erasable PLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PECL_RX | 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:CMOS PECL Receiver |
| PECL_RX_C3 | 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:CMOS PECL Receiver |
| PECL10-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| PECL10-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| PECL10-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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