
AN-SETS-5
PECL Driver
ADVANCED COMMUNICATIONS
APPLICATION NOTE
Revision 2.0/August 2001 Semtech Corp.
Page 5
www.semtech.com
5
Interface Recommendations
The following table gives the input level specifications for some interface chips which may need to be driven by the
CMOS PECL output stages.
Notes: (i) This is a specification relaxation from an original figure of VDD-1V.
Using a standard termination of 50ohm to VDD-2V the CMOS PECL drivers will just comply with the input specifications
of all the above chips apart from the SK100E111.
In order to have a general solution that will satisfy all four chips, the following termination scheme is proposed:
200ohm from the output to Ground.
100ohm to VDD-1.65V (at VDD=3.3V). This can be achieved with a 200ohm resistor from the output to VDD plus
This will give the following output level range over the whole process and temperature range and for supply voltages
between 3V and 3.6V
Note that since the termination resistance is now 100ohm that any long connection runs should be implemented with
100ohm stripline on the PCB instead of the usual 50ohm.
The following plot shows operation at 155MHz with the above termination under typical conditions.
Table 5.1
Input Levels for Specific devices
Device
Symbol
Min
Max
Units
SK1500
Vih
VDD-1.25
(1)
VDD
V
Vil
0
VDD-0.2
V
SK1900
Vih
VDD-1.25
(1)
VDD
V
Vil
0
VDD-0.2
V
SK100LVE111
Vih
VDD-1.165
VDD-0.88
V
Vil
VDD-1.81
VDD-1.475
V
ACS8941
Vih
1.6
VDD
V
Vil
0
VDD
V
Table 5.2
Output Level Range for Proposed Termination Scheme
Parameter
Symbol
Min
Typ
Max
Units
Driver High
Voh
VDD-1.15
VDD-1.1
VDD-0.85
V
Driver Low
Vol
VDD-1.8
VDD-1.65
VDD-1.5
V