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參數(shù)資料
| 型號： | PEDL9352-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 128-Channel Organic EL Driver with Built-in RAM |
| 中文描述： | 128通道有機EL帶內(nèi)置驅(qū)動器在RAM |
| 文件頁數(shù)： | 2/53頁 |
| 文件大?。?/td> | 302K |
| 代理商： | PEDL9352-01 |
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PEDL9352-01
OKI Semiconductor
ML9352
10/53
Line address circuit
The line address circuit is used for specifying the line address corresponding to the COM output when displaying
the contents of the display data RAM as is shown in Figures 4-1 to 4-10. The address line is specified depending
on whether or not a fixed display line is set.
The display area when a fixed display line is not set is equivalent to the number of display lines that are specified to
the increment direction of the line address from the specified scroll start address.
When the line address exceeds 1FH, it returns to 00H.
It is possible to carry out screen scrolling and page changing by changing the line address using the scroll start line
address set command.
The display area when a fixed display line is specified is equivalent to the number of lines which are calculated by
subtracting the number of fixed display lines from the number of display lines that are specified to the increment
direction of the line address from the scroll start line address.
When the line address exceeds 1FH, it returns to the address next to the fixed display line specified.
It is possible to carry out screen scrolling except the fixed display line by changing the line address using the scroll
start line address set command.
Display data latch circuit
The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being
output to the organic EL drive circuits. Since the commands for selecting normal/reverse display and turning the
display ON/OFF control the data in this latch, the data in the display data RAM will not be changed.
Oscillator circuit
This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when CLS = “L”.
The oscillations will be stopped when CLS = “H”, and the display clock has to be input to the CL pin. The
oscillations will also be stopped during the power save mode.
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