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參數(shù)資料
| 型號： | PEEL22LV10AZP-35 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Programmable Electrically Erasable Logic Device |
| 中文描述： | 的CMOS電可擦除可編程邏輯器件 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 146K |
| 代理商： | PEEL22LV10AZP-35 |
1
Commercial/Industrial
04-02-037D
PEEL 22LV10AZ-25 / I-35
CMOS Programmable Electrically Erasable Logic Device
Features
Low Voltage, Ultra Low Power Operation
- Vcc = 2.7 to 3.6 V
- Icc = 5 μA (typical) at standby
- Icc = 1.5 mA (typical) at 1 MHz
- Meets JEDEC LV Interface Spec (JESD8-B)
- 5 Volt tolerant inputs and I/O’s
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super set of standard PLDs
- Pin and JEDEC compatible with 22V10
- Ideal for battery powered systems
- Replaces expensive oscillators
General Description
The PEEL22LV10AZ is a Programmable Electrically
Erasable Logic (PEEL) SPLD (Simple Programmable
Logic Device) that operates over the supply voltage
range of 2.7V-3.6V and features ultra-low, automatic
"zero" power-down operation. The PEEL22LV10AZ is
logically
and
functionally
PEEL22CV10A and PEEL22CV10AZ. The "zero power"
(25
μ
A max. I
CC
) power-down mode makes the
PEEL22LV10AZ ideal for a broad range of battery-
powered portable equipment applications, from hand-
held
meters
to
PCMCIA
reprogrammability provides both the convenience of
product fast reprogramming for product development
and quick personalization in manufacturing, including
Engineering Change Orders.
Architectural Flexibility
- Enhanced architecture fits in more logic
- 133 product terms x 44 input AND array
- 12 inputs and 10 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear, synchronous preset
- Independent output enables
- Programmable clock; pin 1 or p-term
- Programmable clock polarity
- 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC
- Schmitt triggers on clock and data inputs
Schmitt Trigger Inputs
- Eliminates external Schmitt trigger devices
- Ideal for encoder designs
similar
to
ICT's
5V
modems.
EE-
The differences between the PEEL22LV10AZ and
PEEL22CV10A include the addition of programmable
clock polarity, p-term clock, and Schmitt trigger input
buffers on all inputs, including the clock. Schmitt trigger
inputs allow direct input of slow signals such as
biomedical and sine waves or clocks. Like the
PEEL22CV10A, the PEEL22LV10AZ is a pin and
JEDEC compatible, logical superset of the industry
standard
PAL22V10
SPLD
PEEL22LV10AZ
provides
features that allow more logic to be incorporated into
the design. The PEEL22LV10AZ architecture allows it
to replace over twenty standard 24-pin DIP, SOIC,
TSSOP
and
Figure
1.
The
additional
architectural
PLCC
packages.
Figure 1 - Pin Configuration
I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
DIP
1
2
3
4
5
6
7
12
11
10
9
8
24
23
22
21
20
19
18
17
16
15
14
13
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
12
11
10
9
8
I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TSSOP
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
12
11
10
9
8
I
VCC
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
24
23
22
21
20
19
18
17
16
15
14
13
SOIC
PLCC
I
I
I
G
I
I
N
I
I
I
I
I
I
NC
I
I
I
I
I
V
N
I/O
NC
I/O
I/O
I/O
I/O
I/O
5
6
7
8
9
10
11
2
4
26
28 27
1
3
24
23
22
21
20
19
25
18
17
16
14
13
12
15
Figure 2 - Block Diagram
PEEL
TM
"AND"
ARRAY
133 Terms
X
44 Inputs
SP
AC
OE
MACRO
CELL
I/CLK
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
SP = SYNCHRONOUS PRESET
AC = ASYNCHRONOUS CLEAR
OE = OUTPUT ENABLE
CLK MUX (Optional)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PEEL22LV10AZPI-25 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL22LV10AZS-35 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL22LV10AZSI-25 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL22LV10AZT-35 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL22LV10AZTI-25 | CMOS Programmable Electrically Erasable Logic Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEEL22LV10AZPI-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Programmable Electrically Erasable Logic Device |
| PEEL22LV10AZPI-35 | 功能描述:SPLD - 簡單可編程邏輯器件 12 INP 10 I/O 35ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL22LV10AZPI-35L | 功能描述:SPLD - 簡單可編程邏輯器件 12 Input 10 I/O 35ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL22LV10AZS-25 | 功能描述:SPLD - 簡單可編程邏輯器件 12 INP 10 I/O 25ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL22LV10AZS-25L | 功能描述:SPLD - 簡單可編程邏輯器件 12 Input 10 I/O 25ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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