參數(shù)資料
型號(hào)： PEF24622
英文描述： ?SOCRATES-4?
中文描述： ？蘇格拉底- 4？
文件頁數(shù)： 20/73頁
文件大小： 1618K
代理商： PEF24622
PEB 2466
PEF 2466
Functional Description
Hardware Reference Manual
11
2001-02-20
Figure 4
SICOFI
4-μC Block Diagram
Figure 4
shows the functional blocks and the interface pins of the SICOFI
4-μC:
Four independent bi-directional voice channels;
Oversampling sigma-delta A/D and D/A converters with excellent resolution, dynamic
range, linearity, accuracy and signal-to-noise performance;
Hardware filters for decimation and interpolation of the ADC and DAC bit stream, and
pre-processing of the voice data to reduce the load of the DSP;
DSP core with programmable, channel-independent filter structures for impedance
matching, transhybrid balancing, frequency correction and level adjustments;
Configurable A-Law or μ-Law compressor and expander units;
Two PCM ports with data rates from 128 kbps to 8 Mbps per highway;
Programmable time slot assignment for each channel;
twenty-eight signaling input and output pins, accessible through registers;
On-chip PLL for an internal 16.384 MHz clock;
Two programmable versatile clock outputs;
Eight common configuration registers (XR-Registers) affecting all four channels;
Four sets of six channel-specific registers (CR-Registers); and
Coefficient RAM (CRAM) for filter coefficients storage for each channel.
PEB 2466, SICOFI4-μC
PCM-
Interface
with
Time Slot
Assignment
ADC
DAC
Programmable
Filters and Gain
Hardware
Filters
Digital Signal Processing
ADC
DAC
Programmable
Filters and Gain
Hardware
Filters
A-Law
or
μ-Law
ADC
DAC
Programmable
Filters and Gain
Hardware
Filters
ADC
DAC
Programmable
Filters and Gain
Hardware
Filters
Signaling Interface
Serial Microcontroller Interface
Compander
A-Law
or
μ-Law
A-Law
or
μ-Law
A-Law
or
μ-Law
V
IN1
V
OUT1
V
IN2
V
OUT2
V
IN3
V
OUT3
V
IN4
V
OUT4
FSC
PCLK
DXA
DRA
TCA#
Highway A
DXB
DRB
TCB#
Highway B
DOUT
DIN
CS#
DCLK
INT12
INT34
Registers and CRAM
SIx_y
SOx_y
SBx_y
PLL,
Clocking
MCLK
CHCLK2
CHCLK1
2466_205
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