參數(shù)資料
型號(hào): PEF3452
廠商: INFINEON TECHNOLOGIES AG
英文描述: Line Interface Unit for DS3, STS 1 and E3
中文描述: 線路接口單元的DS3中,STS 1和E3
文件頁數(shù): 12/71頁
文件大?。?/td> 1372K
代理商: PEF3452
Preliminary Data Sheet
2
2001-12-05
Type
PEF 3452 H V1.3
Package
P-M
Q
FP-44-2
Line Interface Unit for DS3, STS1 and E3
TE3-LIU
PEF 3452
Version 1.3
PRELIMINARY
1.1
Features
Generic analog interface for all DS3/STS-1/E3
applications
Single chip solution for receive and transmit direction
3.3 V low power device
Integrated receive equalization network
Integrated noise and crosstalk filter
Clock and data recovery using an integrated PLL
with ultra-low intrinsic jitter
Transmit clock duty cycle correction PLL
No external components required for clock and data
recovery and receive equalizer
DSX receive line monitor (additional 20 dB gain according to ANSI T1.102)
Low transmitter output impedances for high transmit return loss
Disable function of the analog transmit line outputs
Transmit pulse shaper to fulfill requirements of ANSI T1.404,
Telcordia GR-499-CORE, ANSI T1.102 and ITU-T G.703 (E3)
Maximum line length up to 1100 ft. (using standard coaxial cable, for example AT
&
T
728A, 734A or 734D)
External line length selection (LBO) is not required
Jitter specifications of GR-499-CORE and ITU-T G.823 are met
Integrated jitter attenuation PLL and buffer in transmit direction
Dual or single rail digital inputs and outputs from/to the framer interface
Selectable line codes (HDB3 (E3), B3ZS (DS3/STS-1), AMI)
Analog and digital loss of signal detection and indication
Automatic RDOP/RDON blanking option in case of LOS
Bipolar violation indication
Local loop and remote loop for diagnostic purposes
Insertion of alarm indication signal (
"
all ones
"
)
Flexible hardware or software controlled device configuration
Device power down function
P-MQFP-44-2
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