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| 型號(hào)： | PEF3452 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Line Interface Unit for DS3, STS 1 and E3 |
| 中文描述： | 線路接口單元的DS3中，STS 1和E3 |
| 文件頁(yè)數(shù)： | 18/71頁(yè) |
| 文件大?。?/td> | 1372K |
| 代理商： | PEF3452 |
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PEF 3452
TE3-LIU V1.3
Pin Descriptions
Preliminary Data Sheet
8
2001-12-05
PRELIMINARY
2.2
Pin Definitions and Functions
Table 1
Interface Pin Functions
Pin No.
Symbol
Input
(
I
)
Output
(
O
)
Supply
(
S
)
Receive Direction
I (analog)
Function
9
RL1
Line Receiver 1
Analog input from the external transformer
(receive bipolar ring).
The signal at RL1 mustbe coded according
to B3ZS or HDB3.
Line Receiver 2
Analog input from the external transformer
(receive bipolar tip).
The signal at RL1 mustbe coded according
to B3ZS or HDB3.
Receive Data Output/Positive
Received data at RL1/2 is sent on RDOP/
RDON to the framer interface. Data is
clocked with the rising or falling edge of
RCLK, depending on RPE.
In single rail mode (DR/SR
=
0), data is sent
in NRZ format.
Receive Data Output/Negative
If dual rail data format is selected, the
negative data signal is output on RDON/
BPV.
B
ipolar Violation
If single rail data format is selected, the
bipolar violation indication signal is output
on RDON/BPV. BPV is synchronized on
RCLK.
Receive Clock
Receive Clock extracted from the incoming
data pulses. The active clock edge is
determined by RPE.
During LOS, a clock signal is generated
internally and driven on RCLK (derived
from REFCLK).
10
RL2
I (analog)
25
RDOP
O
24
RDON
O
BPV
26
RCLK
O
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