參數(shù)資料
型號(hào): PEF81912F
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Power Factor Controller; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C
中文描述: ?2B1Q第二代模塊化綜合業(yè)務(wù)數(shù)字網(wǎng)新臺(tái)幣(智能擴(kuò)展)?
文件頁(yè)數(shù): 137/276頁(yè)
文件大小: 3611K
代理商: PEF81912F
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PEF 81912/81913
Functional Description
Data Sheet
121
2001-03-30
RME
(
R
eceive
M
essage
E
nd) interrupt, indicating that the reception of one message
has been completed and the message has been stored in the RFIFO.
Either
– a short message has been received
(message length
the defined block size (EXMR.RFBS) or
– the last part of a long message has been received
(message length
>
the defined block size (EXMR.RFBS)).
RFO
(
R
eceive
F
rame
O
verflow) interrupt, indicating that a complete frame could not
be stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the
host fails to respond quick enough to RPF/RME interrupts since previous data was not
read by the host.
There are two control commands that are used with the reception of data:
RMC
(
R
eceive
M
essage
C
omplete) command, telling the Q-SMINT
IX that a data
block has been read from the RFIFO and the corresponding FIFO space can be
released for new receive data.
RRES
(
R
eceiver
R
eset) command, resetting the HDLC receiver and clearing the
receive FIFO of any data (e.g. used before start of reception). It has to be used after
a change of the message transfer mode. RRES does not clear pending interrupt
indications of the receiver, but have to be be cleared by reading these interrupts.
Note: The significant interrupts and commands are underlined as only these are usually
used during a normal reception sequence.
The following description of the receive FIFIO operation is illustrated in
Figure 57
for a
RFIFO block size (threshold) of 16 and 32 bytes.
The RFIFO requests service from the microcontroller by setting a bit in the ISTAH
register, which causes an interrupt (RPF, RME, RFO). The microcontroller then reads
status information (RBCH,RBCL), data from the RFIFO and changes the RFIFO block
size (EXMR.RFBS). A block transfer is completed by the microcontroller via a receive
message complete (CMDR.RMC) command. This causes the space of the transferred
bytes being released for new data and in case the frame was complete (RME) the reset
of the receive byte counter RBC (RBCH,RBCL).
1)
The total length of the frame is contained in the RBCH and RBCL registers which contain
a 12 bit number (RBC11...0), so frames up to 4095 byte length can be counted. If a frame
is longer than 4095 bytes, the RBCH.OV (overflow) bit will be set. The least significant
bits of RBCL contain the number of valid bytes in the last data block indicated by RME
(length of last data block
selected block size).
Table 32
shows which RBC bits contain
the number of bytes in the last data block or number of complete data blocks,
1)
If RMC is omitted, then no new interrupt can be generated.
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