- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369993 > pentium II cpu with mobile (Intel Corp.) pentium II processor With On-die Cache Mobile Module Connector 2 (MMC-2)(帶緩存和連接器2的奔II處理器) PDF資料下載
參數(shù)資料
| 型號： | pentium II cpu with mobile |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II processor With On-die Cache Mobile Module Connector 2 (MMC-2)(帶緩存和連接器2的奔II處理器) |
| 中文描述： | 奔騰II處理器芯片上緩存手機模塊連接器2（絲裂霉素2）（帶緩存和連接器2的奔二處理器） |
| 文件頁數(shù)： | 13/48頁 |
| 文件大?。?/td> | 537K |
| 代理商： | PENTIUM II CPU WITH MOBILE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Intel
a
Pentium
a
II Processor With On-Die Cache Mobile Module MMC-2
13
3.1.6
Processor/PIIX4E/M Sideband (8 Signals)
Table 6 lists the signals for the processor and the PIIX4E/M
sideband signals. The voltage level for these signals is
determined by V_CPUPU.
Table 6. Processor/PIIX4E/M Sideband Signal Descriptions
Voltage
Name
Type
Description
FERR#
O
CMOS
V_CPUPU
Numeric Coprocessor Error:
This pin functions as a FERR# signal supporting
coprocessor errors. This signal is tied to the coprocessor error signal on the processor
and is driven by the processor to the PIIX4E/M.
IGNNE#
I D
CMOS
I D
CMOS
I D
CMOS
I D
CMOS
V_CPUPU
Ignore Error:
This open-drain signal is connected to the Ignore Error pin on the
processor and is driven by the PIIX4E/M.
INIT#
V_CPUPU
Initialization:
INIT# is asserted by the PIIX4E/M to the processor for system
initialization. This signal is an open-drain.
INTR
V_CPUPU
Processor Interrupt:
INTR is driven by the PIIX4E/M to signal the processor that an
interrupt request is pending and needs to be serviced. This signal is an open-drain.
NMI
V_CPUPU
Non-maskable Interrupt:
NMI is used to force a non-maskable interrupt to the
processor.
The PIIX4E/M ISA bridge generates a NMI when either SERR# or IOCHK# is
asserted, depending on how the NMI Status and Control Register is programmed. This
signal is an open-drain.
A20M#
I D
CMOS
I D
CMOS
V_CPUPU
Address Bit 20 Mask:
When enabled, this open-drain signal causes the processor to
emulate the address wraparound at one MB, which occurs on the Intel 8086 processor.
SMI#
V_CPUPU
System Management Interrupt:
SMI# is an active low synchronous output from the
PIIX4E/M that is asserted in response to one of many enabled hardware or software
events.
The SMI# open-drain signal can be an asynchronous input to the processor.
However, in this chip set SMI# is synchronous to PCLK.
STPCLK#
I D
CMOS
V_CPUPU
Stop Clock:
STPCLK# is an active low synchronous open-drain output from the
PIIX4E/M that is asserted in response to one of many hardware or software events.
STPCLK# connects directly to the processor and is synchronous to PCICLK.
When the
processor samples STPCLK# asserted, it responds by entering a low power state (Quick
Start). The processor will only exit this mode when this signal is deasserted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium II cpu | Pentium II Processor AT 450MHZ(工作頻率450兆赫茲奔II處理器) |
| pentium II processor | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。