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參數(shù)資料
| 型號： | PHD6N10E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | PowerMOS transistor |
| 中文描述： | 6.3 A, 100 V, 0.54 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | PLASTIC PACKAGE-3 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 70K |
| 代理商： | PHD6N10E |
Philips Semiconductors
Product specification
PowerMOS transistor
PHD6N10E
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermalcyclingperformancewithlow
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general
purpose
applications.
enhancement
mode
SYMBOL
PARAMETER
MAX.
UNIT
V
DS
I
D
P
tot
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
100
6.3
50
0.54
V
A
W
switching
PINNING - SOT428
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
I
D
Continuous drain current
CONDITIONS
T
mb
= 25 C; V
GS
= 10 V
T
mb
= 100 C; V
GS
= 10 V
T
mb
= 25 C
T
mb
= 25 C
T
mb
> 25 C
MIN.
-
-
-
-
-
-
-
MAX.
6.3
4.5
25
50
0.33
±
30
30
UNIT
A
A
A
W
W/K
V
mJ
I
DM
P
D
P
D
/
T
mb
Linear derating factor
V
GS
Gate-source voltage
E
AS
Single pulse avalanche
energy
I
AS
Peak avalanche current
Pulsed drain current
Total dissipation
V
DD
≤
50 V; starting T
j
= 25C; R
GS
= 50
;
V
GS
= 10 V
V
DD
≤
50 V; starting T
j
= 25C; R
GS
= 50
;
V
GS
= 10 V
-
6.3
A
T
j
, T
stg
Operating junction and
storage temperature range
- 55
175
C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
TYP.
-
MAX.
3
UNIT
K/W
R
th j-a
pcb mounted, minimum
footprint
50
-
K/W
1
2
3
tab
d
g
s
September 1997
1
Rev 1.000
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