參數(shù)資料
型號(hào): PHN210T
英文描述: TRANSISTOR | MOSFET | MATCHED PAIR | N-CHANNEL | 27V V(BR)DSS | 3.4A I(D) | SO
中文描述: 晶體管| MOSFET | MATCHED PAIR | N-CHANNEL | 27V V(BR)DSS | 3.4A I(D) | SO封裝
文件頁(yè)數(shù): 5/7頁(yè)
文件大?。?/td> 84K
代理商: PHN210T
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOS
TM
transistor
PHN210T
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
, C
, C
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
) versus avalanche time (t
p
);
unclamped inductive load
0
1
2
3
4
5
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
typ
min
max
0
1
2
3
4
5
6
7
8
9
10
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
Drain-Source Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
150 C
VGS = 0 V
10
100
1000
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
PHN210
0.1
1
10
1E-06
1E-05
1E-04
1E-03
1E-02
Avalanche time, tp (s)
Non-repetitive Avalanche current, IAS (A)
25 C
VDS
ID
tp
Tj prior to avalanche =125 C
0
1
2
3
4
5
6
7
8
9
10
12
14
0
1
2
3
4
5
6
7
8
9
10
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 2.3A
Tj = 25 C
VDD = 15 V
March 1999
5
Rev 1.000
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