參數(shù)資料
型號: PI2EQX4402DNBE
廠商: Pericom
文件頁數(shù): 4/8頁
文件大?。?/td> 0K
描述: IC PCI-E REPEATER 84LFBGA
標準包裝: 260
類型: 轉(zhuǎn)發(fā)器
Tx/Rx類型: CML
電源電壓: 1.7 V ~ 1.9 V
安裝類型: 表面貼裝
封裝/外殼: 84-LFBGA
供應商設備封裝: 84-LFBGA(9x9)
包裝: 托盤
4
PS8873B
11/16/06
PI2EQX4402D
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
with Signal Detect feature
Output Swing Control
SEL3_[A:D]
SEL4_[A:D]
Swing
00
1x
0
1
0.8x
1
0
1.2x
1
1.4x
Equalizer Selection
SEL0_[A:D]
SEL1_[A:D]
SEL2_[A:D]
Compliance Channel
0
No Equalization
0
1
[0:1.5dB] @ 1.25 GHz
0
1
0
[0:2.5dB] @ 1.25 GHz
0
1
[0:3.5dB] @ 1.25 GHz
1
0
[0:4.5dB] @ 1.25 GHz
1
0
1
[0:5.5dB] @ 1.25 GHz
1
0
[0:6.5dB] @ 1.25 GHz
1
[0:7.5dB] @ 1.25 GHz
Output De-emphasis Adjustment
SEL5_[A:D]
SEL6_[A:D]
De-emphasis
0
0dB
0
1
-2.5dB
1
0
-3.5dB
1
-4.5dB
Pin Description (Continued)
Pin #
Pin Name
I/O
Description
GI
DO+
O
Positive CMLOutput Channel D with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
HI
DO-
O
Negative CMLOutput Channel D with internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
A9, A10, B9, C9
EN_
[A,B,C,D]
I
EN_[A:D] is the enable pin with internal 50KΩ pull up resistor. A LVCMOS high
provides normal operation. A LVCMOS low selects a low power down mode.
H6
CKIN-
I
Differential Input Reference Clock
H5
CKIN+
I
K5, K6
OUT0+,
OUT0-
O
Differential Reference Clock Output
K7, K8
OUT1+,
OUT1-
O
J7
IREF
O
External 475Ω resistor connection to set the differential output current
K1
EN_CLK
I
Enable output clock pin with internal 50kΩ pull up resistor. When EN_CLK is
LVCMOS high level, the clock output operates normally. When EN_CLK = low,
the clock outputs are turned off for power savings. A clock is not required by the
data channels for operation.
A1, A2, B2, C2
SD_x
N/A
Signal detected, channels A, B, C, D. Indicated a valid signal level on the channels
input pin pair when active high. When low, SD indicates the input signal level is
below the signal detect threshold level.
Inputs
Outputs
EN_[A, B, C, D]
O+ / O-
High
Normal output
Low
No output
Inputs
Clock Outputs
EN_CLK
High
Clock output
Low
No clock output
06-0306
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