參數(shù)資料
型號(hào): PI6C21200AE
廠商: Pericom
文件頁(yè)數(shù): 1/14頁(yè)
文件大?。?/td> 0K
描述: IC 1:12 CLOCK DVR PCI-EX 56TSSOP
產(chǎn)品培訓(xùn)模塊: Total Timing Technology
標(biāo)準(zhǔn)包裝: 35
系列: PCI Express® (PCIe)
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: PCI Express(PCIe)
輸入: HCSL
輸出: HCSL
電路數(shù): 1
比率 - 輸入:輸出: 1:12
差分 - 輸入:輸出: 是/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 管件
1
PS8820B
10/14/09
Features
Twelve Pairs of PCIe Differential Clocks (HCSL compatible
signaling)
Low skew < 50ps
Low jitter < 50ps
Output Enable for all outputs
Outputs tristate control via SMBus
Power Management Control
Programmable PLL Bandwidth
PLL or Fan out operation
Gear Ratio supporting different output frequencies
3.3V Operation
56-pin Package (Pb-Free & Green):
- TSSOP (A56)
Description
PI6C21200 is a high-speed, low-noise PCIe differential
clock buffer designed to be a companion with PI6C410B clock
synthesizer. The device distributes twelve copies of the
differential SRC clock coming from PI6C410B. The output
frequency can be ratioed to offer a derivative frequency from
the input frequency. Each differential output is controlled by
individual OE pin, except OUT10 and OUT11 are sharing one
OE_10#_11# pin. The clock outputs are controlled by input selec-
tion of SA_0, SA_1, SA_2 via SMBus, SCLK and SDA.
Block Diagram
Pinout Diagram
PI6C21200
1:12 Clock Driver for Intel PCIe Chipsets
OUT0
OUT0#
OUT2
OUT2#
OUT1
OUT1#
OUT3
OUT3#
OUT4
OUT4#
OUT5
OUT5#
OUT6
OUT6#
OUT7
OUT7#
OUT8
OUT8#
OUT9
OUT9#
OUT10
OUT10#
OUT11
OUT11#
HIGH_BW#
PLL
SRC
SCR#
SA_2 /
PLLBypass#
SA_[0:1]
SCLK
SDA
OE [0:10]#
VTT_PWRGD#
/ PWRDWN
SMBus
Controller
Output
Control
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
HIGH_BW#
SRC_IN
SRC_IN#
SA_0
OE_0#
OUT0
OUT0#
OE_1#
OUT1
OUT1#
VDD
VSS
OUT2
OUT2#
OE_2#
OUT3
OUT3#
OE_3#
OUT4
OUT4#
OE_4#
VDD
VSS
OUT5
OUT5#
OE_5#
SA_1
SDA
VDD_A
VSS_A
IREF
OE_10#_11#
OUT11
OUT11#
VDD
VSS
OUT10
OUT10#
FS_A
VTT_PWRGD# / PWRDWN
OE_9#
OUT9
OUT9#
OE_8#
OUT8
OUT8#
VDD
VSS
OUT7
OUT7#
OE_7#
OUT6
OUT6#
OE_6#
SA_2 /PLLBypass#
SCL
09-0003
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