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參數(shù)資料
| 型號(hào)： | PI6C2501W |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | Phase-Locked Loop Clock Driver |
| 中文描述： | 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | PI6C2501W |
1
PS8381A 07/17/00
Product Pin Configuration
Logic Block Diagram
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Phase-Locked Loop Clock Driver
Product Features
High-Performance, Phase-Locked-Loop Clock Distribution
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
Zero Input-to-Output delay
Low jitter: Cycle-to-Cycle jitter ±100ps max.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V V
CC
Wide range of Clock Frequencies up to 80 MHz
Package: Plastic 8-pin SOIC (W)
Product Description
The PI6C2501 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the CLK_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to CLK_OUT output will be nearly zero.
Application
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers, such as the
PI6C2509Q, or PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends using a zero-delay buffer and
an eighteen output non-zero-delay buffer. As shown in Figure 1,
this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clock Signal and 17 Outputs
17
Zero Delay
Buffer
PI6C2501
Reference
Clock
Signal
Feedback
CLK_OUT
18 Outputs
Non-PLL
Buffer
V
C
1
2
3
4
VCC
CLK_OUT
CLK_IN
AVCC
GND
FB_IN
8
7
6
5
AGND
GND
8-Pin
W
CLK_IN
FB_IN
PLL
AV
CC
CLK_OUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6C2502A | Phase-Locked Loop Clock Driver |
| PI6C2502AW | Phase-Locked Loop Clock Driver |
| PI6C2502 | Phase-Locked Loop Clock Driver |
| PI6C2502W | SMBus Dual High-SideSwitch Controller; Package: MSOP; No of Pins: 8; Temperature Range: 0°C to +70°C |
| PI6C2504A | Phase-Locked Loop Clock Driver with 4 Clock Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C2501WE | 功能描述:鎖相環(huán) - PLL 3.3v PLL Clock Drivr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2501WEX | 功能描述:鎖相環(huán) - PLL 3.3v PLL Clock Drivr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2502 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver |
| PI6C2502A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver |
| PI6C2502AW | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 80MHz to 134MHz 8-Pin SOIC |
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