參數(shù)資料
型號: PI74SSTVF16859AZBE
廠商: Pericom
文件頁數(shù): 7/8頁
文件大小: 0K
描述: IC REG BUFFER 13-26BIT 56-QFN
產(chǎn)品變化通告: Product Discontinuation Notice 11/Feb/2008
標準包裝: 348
系列: 74SSTVF
邏輯類型: 13 位至 26 位寄存緩沖器,DDR
電源電壓: 2.3 V ~ 2.7 V
位數(shù): 13,26
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-QFN-EP(8x8)
包裝: 托盤
7
PS8684B
10/30/06
PI74SSTVF16859A
13-Bit to 26-Bit Registered Buffer
Voltage and Current Waveforms
InputActiveandInactiveTimes
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
Test Circuit and Switching Waveforms
Notes:
8.
CL includes probe and jig capacitance.
9.
IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.
10. All input pulses are supplied by generators having the following characteristics: PRR
≤10 MHz, ZO = 50 ohms.
Input slew rate = 1V/ns ±20% (unless otherwise specified).
11. The outputs are measured one at a time with one transition per measurement.
12. VTT = VREF = VDDQ/2
13. VIH = VREF + 310mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input.
14. VIL = VREF –310mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input.
15. tPLH and tPHL are the same as tpd.
Parameter Measurement Information
LoadCircuit
Input
VIL
VREF
tw
VIH
Input
Timing
Input
th
tsu
VIL
VICR
VREF
VI(PP)
VIH
Voltage Waveforms - Propagation Delay Times
Timing
Input
Output
VICR
tPLH
tPHL
VICR
VI(PP)
VOH
VTT
VOL
LVCMOS
RESET
Input
Output
tPHL
VDD/2
VOH
VIH
VIL
VTT
VOL
Voltage Waveforms - Propagation Delay Times
LVCMOS
RESET
Input
IDD(9)
VDD
VDD/2
tinact
0V
IDDH
10%
90%
IDDL
tact
500
Ω
From Output
Under Test
CL = 30pF(8)
Test Point
06-0288
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