參數(shù)資料
型號(hào)： PI7C8150B-33
英文描述： PCI Bridge | Asynchronous 2-Port PCI Bridge
中文描述： PCI橋|異步2端口PCI橋
文件頁數(shù)： 16/115頁
文件大小： 879K
代理商： PI7C8150B-33
PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 16 of 115
July 31, 2003 – Revision 1.031
Name
S_CLKIN
Pin #
21
Pin #
H3
Type
I
Description
Secondary Clock Input:
Provides timing for all
transactions on the secondary interface.
Secondary Clock Output:
Provides secondary clocks
phase synchronous with the P_CLK in synchronous
mode.
When these clocks are used, one of the clock outputs
must be fed back to S_CLKIN. Unused outputs may be
disabled by:
1. Writing the secondary clock disable bits in the
configuration space
2. Using the serial disable mask using the GPIO pins and
MSK_IN
3. Terminating them electrically.
In asynchronous mode, S_CLKOUT[5:0] are derived
from MSK_IN / ASYNC_CLKIN (please see CFG66 /
SCAN_EN_H / CLK_RATE pin description).
S_CLKOUT[9:0]
42, 41, 39, 38, 36,
35, 33, 32, 30, 29
M3, M2, N1,
L4, L3, M1, L2,
L1, K3, K2
O
2.2.4
MISCELLANEOUS SIGNALS
Name
MSK_IN /
ASYNC_CLKIN
Pin #
126
Pin #
K15
Type
I
Description
This is a multiplexed pin that is MSK_IN in
synchronous mode and ASYNC_CLK_IN in
asynchronous mode. This pin has a weak internal pull-
down resistor.
MSK_IN - Secondary Clock Disable Serial Input
(synchronous mode):
This pin is used by PI7C8150B to
disable secondary clock outputs. The serial stream is
received by MSK_IN, starting when P_RESET is
detected deasserted and S_RESET_L is detected as
being asserted. The serial data is used for selectively
disabling secondary clock outputs and is shifted into the
secondary clock control configuration register. This pin
can be tied LOW to enable all secondary clock outputs
or tied HIGH to drive all the secondary clock outputs
HIGH.
ASYNC_CLKIN – Secondary Clock Input
(asynchronous mode):
The asynchronous clock for the
secondary interface should be connected to this pin in
asynchronous mode. S_CLKOUT[9:0] will be derived
from ASYNC_CLKIN.
Primary I/O Voltage:
This pin is used to determine
either 3.3V or 5V signaling on the primary bus. P_VIO
must be tied to 3.3V only when all devices on the
primary bus use 3.3V signaling. Otherwise, P_VIO is
tied to 5V.
Secondary I/O Voltage:
This pin is used to determine
either 3.3V or 5V signaling on the secondary bus.
S_VIO must be tied to 3.3V only when all devices on
the secondary bus use 3.3V signaling. Otherwise, S_VIO
is tied to 5V.
Bus/Power Clock Control Management Pin:
When
this pin is tied HIGH and the PI7C8150B is placed in the
D3
HOT
power state, it enables the PI7C8150B to place
the secondary bus in the B2 power state. The secondary
clocks are disabled and driven to 0. When this pin is tied
LOW, there is no effect on the secondary bus clocks
when the PI7C8150B enters the D3
HOT
power state.
P_VIO
124
K14
I
S_VIO
135
G14
I
BPCCE
44
N2
I
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150BEVB 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8150BMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMA-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BMAI 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
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