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參數(shù)資料
| 型號： | PI7C8150B-33 |
| 英文描述： | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| 中文描述： | PCI橋|異步2端口PCI橋 |
| 文件頁數(shù)： | 55/115頁 |
| 文件大小： | 879K |
| 代理商： | PI7C8150B-33 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 55 of 115
July 31, 2003 – Revision 1.031
in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally
and accepts transaction if it is directed to or across PI7C8150B.
!
!
PI7C8150B sets the detected parity error bit in the secondary status register.
PI7C8150B asserts P_SERR_L and sets signaled system error bit in status register, if
both of the following conditions are met:
!
The SERR_L enable bit is set in the command register.
!
The parity error response bit is set in the bridge control register.
6.2
DATA PARITY ERRORS
When forwarding transactions, PI7C8150B attempts to pass the data parity condition from
one interface to the other unchanged, whenever possible, to allow the master and target
devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C8150B.
6.2.1
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C8150B detects a data parity error during a Type 0 configuration write
transaction to PI7C8150B configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C8150B asserts
P_TRDY_L and writes the data to the configuration register. PI7C8150B also asserts
P_PERR_L. If the parity error response bit is not set, PI7C8150B does not assert
P_PERR_L.
PI7C8150B sets the detected parity error bit in the status register, regardless of the state of
the parity error response bit.
6.2.2
READ TRANSACTIONS
When PI7C8150B detects a parity error during a read transaction, the target drives data and
data parity, and the initiator checks parity and conditionally asserts PERR_L. For
downstream transactions, when PI7C8150B detects a read data parity error on the
secondary bus, the following events occur:
!
PI7C8150B asserts S_PERR_L two cycles following the data transfer, if the secondary
interface parity error response bit is set in the bridge control register.
!
PI7C8150B sets the detected parity error bit in the secondary status register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8152B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8154 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8154-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMAE | 功能描述:外圍驅(qū)動器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150BMAI | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
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