PIC10(L)F320/322
DS41585A-page 160
Preliminary
2011 Microchip Technology Inc.
TABLE 23-2:
PIC10(L)F320/322 INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f
–
f, d
f
–
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1(2)
1
1(2)
1
00
0111
0101
0001
1001
0011
1011
1010
1111
0100
1000
0000
1101
1100
0010
1110
0110
dfff
lfff
0xxx
dfff
lfff
0xx0
dfff
ffff
xxxx
ffff
0000
ffff
C, DC, Z
Z
C
C, DC, Z
Z
1, 2
2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1 (2)
01
00bb
01bb
10bb
11bb
bfff
ffff
1, 2
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
–
k
–
k
–
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
2
1
2
1
2
1
11
10
00
10
11
00
11
00
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
110x
1010
kkkk
0110
kkkk
0000
kkkk
0000
0110
kkkk
0100
kkkk
1001
kkkk
1000
0011
kkkk
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
Note
1:
When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2:
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3:
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.