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參數(shù)資料
| 型號(hào)： | PIC12F1501-I/MF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 24/33頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 1.75KB FLASH 8-DFN |
| 標(biāo)準(zhǔn)包裝： | 120 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲(chǔ)器容量： | 1.75KB（1K x 14） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VDFN 裸露焊盤 |
| 包裝： | 管件 |
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2007 Microchip Technology Inc.
DS39605F-page 29
PIC18F1220/1320
TABLE 3-3:
ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock in Power
Managed Mode
Primary System
Clock
Power
Managed
Mode Exit
Delay
Clock Ready
Status Bit
(OSCCON)
Activity during Wake-up from
Power Managed Mode
Exit by Interrupt
Exit by Reset
Primary System
Clock
(PRI_IDLE mode)
LP, XT, HS
5-10
μs(5)
OSTS
CPU and peripherals
clocked by primary
clock and executing
instructions.
Not clocked or
Two-Speed Start-up
(if enabled)(3).
HSPLL
EC, RC, INTRC(1)
—
INTOSC(2)
IOFS
T1OSC or
INTRC(1)
LP, XT, HS
OST
OSTS
CPU and peripherals
clocked by selected
power managed mode
clock and executing
instructions until
primary clock source
becomes ready.
HSPLL
OST + 2 ms
EC, RC, INTRC(1)
5-10
μs(5)
—
INTOSC(2)
1ms(4)
IOFS
INTOSC(2)
LP, XT, HS
OST
OSTS
HSPLL
OST + 2 ms
EC, RC, INTRC(1)
5-10
μs(5)
—
INTOSC(2)
None
IOFS
Sleep mode
LP, XT, HS
OST
OSTS
Not clocked or
Two-Speed Start-up (if
enabled) until primary
clock source becomes
ready(3).
HSPLL
OST + 2 ms
EC, RC, INTRC(1)
5-10
μs(5)
—
INTOSC(2)
1ms(4)
IOFS
Note 1:
In this instance, refers specifically to the INTRC clock source.
2:
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3:
Two-Speed Start-up is covered in greater detail in Section 19.3 “Two-Speed Start-up”.
4:
Execution continues during the INTOSC stabilization period.
5:
Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
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