180h(1) INDF0 Addressi" />
參數(shù)資料
型號: PIC12F1840-I/MF
廠商: Microchip Technology
文件頁數(shù): 43/122頁
文件大?。?/td> 0K
描述: MCU 7KB FLASH 256B RAM 8-DFN
產品培訓模塊: 8-bit PIC® Microcontroller Portfolio
標準包裝: 120
系列: PIC® XLP™ 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 4x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-VDFN 裸露焊盤
包裝: 管件
2011 Microchip Technology Inc.
Preliminary
DS41441B-page 27
PIC12(L)F1840
Bank 3
180h(1)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
181h(1)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
182h(1)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
183h(1)
STATUS
—TO
PD
ZDC
C
---1 1000 ---q quuu
184h(1)
FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
185h(1)
FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
186h(1)
FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
187h(1)
FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
188h(1)
BSR
BSR<4:0>
---0 0000 ---0 0000
189h(1)
WREG
Working Register
0000 0000 uuuu uuuu
18Ah(1)
PCLATH
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
18Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 000x 0000 000u
18Ch
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
---1 -111 ---1 -111
18Dh
Unimplemented
18Eh
Unimplemented
18Fh
Unimplemented
190h
Unimplemented
191h
EEADRL
EEPROM/Program Memory Address Register Low Byte
0000 0000 0000 0000
192h
EEADRH
EEPROM / Program Memory Address Register High Byte
1000 0000 1000 0000
193h
EEDATL
EEPROM/Program Memory Read Data Register Low Byte
xxxx xxxx uuuu uuuu
194h
EEDATH
EEPROM / Program Memory Read Data Register High Byte
--xx xxxx --uu uuuu
195h
EECON1
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
0000 x000 0000 q000
196h
EECON2
EEPROM control register 2
0000 0000 0000 0000
197h
VREGCON(2)
—VREGPM
Reserved ---- --01 ---- --01
198h
Unimplemented
199h
RCREG
USART Receive Data Register
0000 0000 0000 0000
19Ah
TXREG
USART Transmit Data Register
0000 0000 0000 0000
19Bh
SPBRGL
Baud Rate Generator Data Register Low
0000 0000 0000 0000
19Ch
SPBRGH
Baud Rate Generator Data Register High
0000 0000 0000 0000
19Dh
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
19Eh
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010 0000 0010
19Fh
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
—WUE
ABDEN
01-0 0-00 01-0 0-00
TABLE 3-7:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
These registers can be addressed from any bank.
2:
PIC12F1840 only.
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