參數(shù)資料
型號(hào)： PIC12F1840-I/MF
廠商： Microchip Technology
文件頁數(shù)： 73/122頁
文件大?。?/td> 0K
描述： MCU 7KB FLASH 256B RAM 8-DFN
產(chǎn)品培訓(xùn)模塊： 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 120
系列： PIC® XLP™ 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 32MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 7KB（4K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 256 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-VDFN 裸露焊盤
包裝： 管件
PIC12(L)F1840
DS41441B-page 54
Preliminary
2011 Microchip Technology Inc.
5.2.2.6
32 MHz Internal Oscillator
Frequency Selection
The Internal Oscillator Block can be used with the 4X
PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz inter-
nal clock source:
The FOSC bits in Configuration Word 1 must be
set to use the INTOSC source as the device sys-
tem clock (FOSC<2:0> = 100).
The SCS bits in the OSCCON register must be
cleared to use the clock determined by
FOSC<2:0> in Configuration Word 1
(SCS<1:0> = 00).
The IRCF bits in the OSCCON register must be
set to the 8 MHz HFINTOSC set to use
(IRCF<3:0> = 1110).
The SPLLEN bit in the OSCCON register must be
set to enable the 4xPLL, or the PLLEN bit of the
Configuration Word 2 must be programmed to a
‘1’.
The 4xPLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4xPLL with the internal oscillator.
5.2.2.7
Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 5-7). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
1.
IRCF<3:0> bits of the OSCCON register are
modified.
2.
If the new clock is shut down, a clock start-up
delay is started.
3.
Clock switch circuitry waits for a falling edge of
the current clock.
4.
The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
5.
The new clock is now active.
6.
The OSCSTAT register is updated as required.
7.
Clock switch is complete.
See Figure 5-7 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.
Start-up delay specifications are located in the
oscillator
tables
of
Note:
When using the PLLEN bit of the
Configuration Word 2, the 4xPLL cannot
be disabled by software and the 8 MHz
HFINTOSC option will no longer be
available.
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