參數(shù)資料
型號: PIC12F1840-I/SN
廠商: Microchip Technology
文件頁數(shù): 107/122頁
文件大?。?/td> 0K
描述: MCU 7KB FLASH 256B RAM 8-SOIC
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準包裝: 100
系列: PIC® XLP™ 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 管件
2011 Microchip Technology Inc.
Preliminary
DS41441B-page 85
PIC12(L)F1840
8.5.3
PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 8-3.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 8-3:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
U-0
R/W-0/0
U-0
OSFIE
C1IE
EEIE
BCL1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSFIE:
Oscillator Fail Interrupt Enable bit
1
= Enables the Oscillator Fail interrupt
0
= Disables the Oscillator Fail interrupt
bit 6
Unimplemented:
Read as ‘0’
bit 5
C1IE:
Comparator C1 Interrupt Enable bit
1
= Enables the Comparator C1 interrupt
0
= Disables the Comparator C1 interrupt
bit 4
EEIE:
EEPROM Write Completion Interrupt Enable bit
1
= Enables the EEPROM Write Completion interrupt
0
= Disables the EEPROM Write Completion interrupt
bit 3
BCL1IE:
MSSP Bus Collision Interrupt Enable bit
1
= Enables the MSSP Bus Collision Interrupt
0
= Disables the MSSP Bus Collision Interrupt
bit 2-0
Unimplemented:
Read as ‘0’
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