參數(shù)資料
型號: PIC12F1840-I/SN
廠商: Microchip Technology
文件頁數(shù): 111/122頁
文件大?。?/td> 0K
描述: MCU 7KB FLASH 256B RAM 8-SOIC
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 100
系列: PIC® XLP™ 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 管件
2011 Microchip Technology Inc.
Preliminary
DS41441B-page 89
PIC12(L)F1840
9.0
POWER-DOWN MODE (SLEEP)
The Power-Down mode is entered by executing a
SLEEP
instruction.
Upon entering Sleep mode, the following conditions
exist:
1.
WDT will be cleared but keeps running, if
enabled for operation during Sleep.
2.
PD bit of the STATUS register is cleared.
3.
TO bit of the STATUS register is set.
4.
CPU clock is disabled.
5.
31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
6.
Timer1 oscillator is unaffected and peripherals
that operate from it may continue operation in
Sleep.
7.
ADC is unaffected, if the dedicated FRC clock is
selected.
8.
Capacitive Sensing oscillator is unaffected.
9.
I/O ports maintain the status they had before
SLEEP
was executed (driving high, low or high-
impedance).
10. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following condi-
tions should be considered:
I/O pins should not be floating
External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins
Current draw from pins with internal weak pull-ups
Modules using 31 kHz LFINTOSC
Modules using Timer1 oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules.
See
for more information on
these modules.
9.1
Wake-up from Sleep
The device can wake-up from Sleep through one of the
following events:
1.
External Reset input on MCLR pin, if enabled
2.
BOR Reset, if enabled
3.
POR Reset
4.
Watchdog Timer, if enabled
5.
Any external interrupt
6.
Interrupts by peripherals capable of running dur-
ing Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of pro-
gram execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 7.10
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP
instruction, the device will call the Interrupt Ser-
vice Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
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