參數(shù)資料
型號: PIC12F519-I/SN
廠商: Microchip Technology
文件頁數(shù): 18/96頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 1KX12 8SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 100
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 1.5KB(1K x 12)
程序存儲器類型: 閃存
RAM 容量: 41 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 637 (CN2011-ZH PDF)
2008 Microchip Technology Inc.
DS41319B-page 23
PIC12F519
6.0
I/O PORT
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
6.1
GPIO
GPIO is an 8-bit I/O register. Only the low-order 6 bits
are used (GP<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s. Please note that GP3 is an input-only
pin. The Configuration Word can set several I/O’s to
alternate functions. When acting as alternate functions,
the pins will read as ‘0’ during a port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also for wake-up on change. The wake-up on
change and weak pull-up functions are not pin select-
able. If GP3/MCLR is configured as MCLR, weak pull-
up is always on and wake-up on change for this pin is
not enabled.
6.2
TRIS Registers
The Output Driver Control registers are loaded with
the contents of the W Register by executing the TRIS
f
instruction. A ‘1’ from a TRISGPIO Register bit puts
the corresponding output driver in a high-impedance
(Input) mode. A ‘0’ puts the contents of the output data
latch on the selected pins, enabling the output buffer.
The TRISGPIO register is “write-only”. Bits <5:0> are
set (output drivers disabled) upon Reset.
TABLE 6-1:
WEAK PULL-UP ENABLED PINS
Note:
If the T0CS bit is set to ‘1’, it will override
the TRISGPIO function on the T0CKI pin.
Pin
WPU
WU
GP0
Y
GP1
Y
GP2
N
GP3
Y(1)
Y
GP4
N
GP5
N
GP6
N
Note 1:
When MCLRE = 1, the weak pull-up on GP3/MCLR is always
enabled.
2:
WPU = Weak pull-up; WU = Wake-up.
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