參數(shù)資料
型號： PIC12F683T-I/MD
廠商： Microchip Technology
文件頁數(shù)： 165/176頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 2KX14 8DFN
產(chǎn)品培訓模塊： Asynchronous Stimulus
Digi-Key 應用說明： AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標準包裝： 3,300
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 5
程序存儲器容量： 3.5KB（2K x 14）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-VDFN 裸露焊盤
包裝： 帶卷 (TR)
配用： AC164326-ND - MODULA SKT PM3 20QFN
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
2007 Microchip Technology Inc.
DS41211D-page 87
PIC12F683
12.3.4
BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word register select one of four BOR modes. Two
modes have been added to allow software or hardware
control of the BOR enable. When BOREN<1:0> = 01,
the SBOREN bit of the PCON register enables/disables
the BOR, allowing it to be controlled in software. By
selecting BOREN<1:0> = 10, the BOR is automatically
disabled in Sleep to conserve power and enabled on
wake-up. In this mode, the SBOREN bit is disabled.
See
for
the
Configuration
Word
definition.
A brown-out occurs when VDD falls below VBOR for
greater than parameter TBOR (see Section 15.0
“Electrical Specifications”). The brown-out condition
will reset the device. This will occur regardless of VDD
slew rate. A Brown-out Reset may not occur if VDD falls
below VBOR for less than parameter TBOR.
On any Reset (Power-on, Brown-out Reset, Watchdog
Timer, etc.), the chip will remain in Reset until VDD rises
above VBOR (see Figure 12-3). If enabled, the
Power-up Timer will be invoked by the Reset and keep
the chip in Reset an additional 64 ms.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
12.3.5
BOR CALIBRATION
The PIC12F683 stores the BOR calibration values in
fuses located in the Calibration Word register (2008h).
The Calibration Word register is not erased when using
the
specified
bulk
erase
sequence
in
the
“PIC12F6XX/16F6XX Memory Programming Specifi-
cation”
(DS41204)
and
thus,
does
not
require
reprogramming.
FIGURE 12-3:
BROWN-OUT SITUATIONS
Note:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
register.
Note:
Address 2008h is beyond the user pro-
gram memory space. It belongs to the
special
configuration
memory
space
(2000h-3FFFh), which can be accessed
only
during
programming.
See
“PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
64 ms(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset
64 ms(1)
< 64 ms
64 ms(1)
VBOR
VDD
Internal
Reset
Note 1:
64 ms delay only if PWRTE bit is programmed to ‘0’.
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