參數(shù)資料
型號： PIC14000-04/SO
廠商： Microchip Technology
文件頁數(shù)： 98/153頁
文件大?。?/td> 0K
描述： IC MCU OTP 4KX14 A/D 28SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 27
系列： PIC® 14
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
連通性： I²C
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 7KB（4K x 14）
程序存儲器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： 斜率 A/D
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
配用： ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1073-ND - ADAPTER 28-SOIC TO 28-SOIC
309-1024-ND - ADAPTER 28-SOIC TO 28-DIP
309-1023-ND - ADAPTER 28-SOIC TO 28-DIP
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 49
PIC14000
7.5.1
SLAVE MODE
In slave mode, the SCLx and SDAx pins must be
congured as inputs (TRISC<7:6> or TRISD<1:0> are
set). The I2C module will override the input state with
the output data when required (slave-transmitter).
When an address is matched or the data transfer from
an
address
match
is
received,
the
hardware
automatically will generate the acknowledge (ACK)
pulse, and then load the I2CBUF with the received
value in the I2CSR.
There are two conditions that will cause the I2C module
not to give this ACK pulse. These are if either (or both)
occur:
the Buffer Full (BF), I2CSTAT<0>, bit was set
before the transfer was received, or
the Overow (I2COV), I2CCON<6> bit was set
before the transfer was received.
In this case, the I2CSR value is not loaded into the
I2CBUF, but the I2CIF bit is set. Table 7-2 shows what
happens when a data transfer byte is received, given
the status of the BF and I2COV bits. The shaded boxes
show the conditions where user software did not
properly clear the overow condition. The BF ag is
cleared by reading the I2CBUF register while the
I2COV bit is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specication as well as the requirement of the I2C
module is shown in the AC timing specications.
TABLE 7-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data Transfer
is Received
BF
I2COV
I2CSR-> I2CBUF
Generate ACK Pulse
Set I2CIF bit
(I2C interrupt if enabled)
0
Yes
1
0
No
Yes
1
No
Yes
0
1
No
Yes
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