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| 型號(hào)： | PIC16C57-XTI/P |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 4/194頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 2KX12 28DIP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 20 |
| 程序存儲(chǔ)器容量： | 3KB（2K x 12） |
| 程序存儲(chǔ)器類(lèi)型： | OTP |
| RAM 容量： | 72 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 6.25 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 配用： | XLT28XP-ND - SOCKET TRANSITION ICE 28DIP AC164001-ND - MODULE SKT PROMATEII 18/28DIP |
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PIC18F2450/4450
2006 Microchip Technology Inc.
Advance Information
DS39760A-page 99
9.0
I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
TRIS register (data direction register)
PORT register (reads the levels on the pins of the
device)
LAT register (output latch)
The Data Latch register (LATA) is useful for read-
modify-write operations on the value driven by the I/O
pins.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 9-1.
FIGURE 9-1:
GENERIC I/O PORT
OPERATION
9.1
PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins; writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA6 pin
is multiplexed with the main oscillator pin; it is enabled
as an oscillator or I/O pin by the selection of the main
oscillator
in
Configuration
Register
1H
(see
Section 18.1 “Configuration Bits” for details). When
not used as a port pin, RA6 and its associated TRIS
and LAT bits are read as ‘0’.
RA4 is also multiplexed with the USB module; it serves
as a receiver input from an external USB transceiver.
For details on configuration of the USB module, see
Several PORTA pins are multiplexed with analog inputs.
The operation of pins RA5 and RA3:RA0 as A/D
converter inputs is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1).
All other PORTA pins have TTL input levels and full
CMOS output drivers.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 9-1:
INITIALIZING PORTA
Data
Bus
WR LAT
WR TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin(1)
Q
D
CK
Q
D
CK
EN
QD
EN
RD LAT
or PORT
Note 1:
I/O pins have diode protection to VDD and VSS.
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
CLRF
LATA
; Alternate method
; to clear output
; data latches
MOVLW
0Fh
; Configure A/D
MOVWF
ADCON1
; for digital inputs
MOVLW
0CFh
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
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